Addressing scheme for accessing a portion of a large memory space

• US 5,386,523 A
• Filed: 01/10/1992
• Issued: 01/31/1995
• Est. Priority Date: 01/10/1992
• Status: Expired due to Term

• Current Assignee: Enterasys Networks Incorporated (Extreme Networks, Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Brash, David L. A., Crook, Neal A., Seaman, Michael J.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US07/818,607
• Time in Patent Office: 1,117 Days
• Field of Search: 395/400
• US Class Current: 711/220
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/342 Extension of operand address space

Abstract

A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together using a boolean operation when generating the address. Using this method, the higher order register can be used to select a segment of the addressable space of the computer system. Then, all accesses to that portion of the addressable space can be controlled by changing only the lower order register. This results in a saving of time since only one of the registers need be reloaded for each subsequent access.

Claims

1. A method of generating an address in a computer system, the address being represented by a first number of address bits, each unique value of the address corresponding to a unique memory location in the computer system, comprising the steps of:

a) loading a first register with binary data, the first register including a first number of register storage locations, the first number of register storage locations being less than the first number of address bits;

b) loading a second register with binary data, the second register including a second number of register storage locations, the second number of register storage locations being less than the first number of address bits;

c) logically combining in a boolean operation a bit in each of a preselected third number of register storage locations of the first register only with a bit in each of a preselected equal number of corresponding register storage locations of the second register to generate an equal number of logical combination result bits;

d) concatenating the logical combination result bits of step c, and binary data in the first and second registers not logically combined in step c to thereby generate the address represented by the first number of address bits.

2. The method of claim 1, further comprising:

e) loading new binary data in the second register only; and

f) changing the address represented by the first number of address bits by repeating steps c and d using the new binary data loaded in the second register.

3. The method of claim 1, wherein the first register includes binary locations for a high order portion of the address and the second register includes binary locations for a low order portion of the address.

4. The method of claim 3, wherein preselected ones of the third number of register storage locations are loaded with binary zero values.

5. The method of claim 4, wherein preselected ones of the third number of register storage locations in the second register are loaded with binary zero values, said preselected register storage locations corresponding to ones of the third number of register storage locations in the first register other than the preselected ones of the register storage locations in the first register which are loaded with binary zero values.

6. The method of claim 5, wherein the binary data of the first register not logically combined in step c correspond to highest order address bits of a segment of memory locations in the computer system.

7. The method of claim 6, wherein in step c, the logically combined binary data is combined using a logical OR function.

8. The method of claim 3, wherein preselected ones of the third number of register storage locations are loaded with binary 1 values.

9. The method of claim 8, wherein the binary data of the first register not logically combined in step c corresponds to highest order address bits of a segment of memory locations in the computer system.

10. The method of claim 3, wherein before step d the method further comprises:

e) loading a third register with binary data as a portion of the address represented by the first number of address bits, the third register including a fourth number of register storage locations, the fourth number of register storage locations being less than the first number of address bits; and

f) wherein step d includes

concatenating the logically combined data of step c, binary data in the third register and binary data in the first and second registers not logically combined in step c to thereby generate the address represented by the first number of address bits.

11. The method of claim 10, wherein in step c, the logically combined binary data is combined using a logical OR function.

12. An apparatus for generating an address to locate a location in a memory, comprising:

a first register having a first number of register storage locations for storage of a first number of address bits;

a second register having a second number of register storage locations for storage of a second number of address bits; and

a logic device coupled to each of the first and second registers for logically combining in a boolean operation a bit in each of a preselected third number of register storage locations of the first register only with a bit in each of a preselected equal number of corresponding register storage locations of the second register to provide an equal number of logically combined address bits;

whereby the address to locate a location in a memory, comprises the logically combined address bits and address bits of the first and second address bits other than the bits of the preselected third number of register storage locations in each of the first and second registers.

13. The apparatus of claim 12, wherein the logic device comprises a set of OR gates.

14. A method of generating an address in a computer system, the address being represented by a first number of address bits, each unique value of the address corresponding to a unique memory location in the computer system, comprising the steps of:

a) loading a first register with binary data, the first register including a first number of register storage locations, the first number of register storage locations being less than the first number of address bits;

b) loading a second register with binary data, the second register including a second number of register storage locations, the second number of register storage locations being less than the first number of address bits;

c) logically combining binary data in a preselected third number of register storage locations of the first register and binary data in an equal number of corresponding register storage locations of the second register, wherein individual binary data from each of the register storage locations of the first register is logically combined in a single boolean operation with individual binary data from each of the corresponding register storage locations of the second register;

d) concatenating the logically combined data of step c, and binary data in the first and second registers not logically combined in step c to thereby generate the address represented by the first number of address bits.