Inter-processor communication method for transmitting data and processor dependent information predetermined for a receiving process of another processor

• US 5,386,566 A
• Filed: 03/18/1992
• Issued: 01/31/1995
• Est. Priority Date: 03/20/1991
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering Corporation
• Original Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering Corporation
• Inventors: Hamanaka, Naoki, Higuchi, Tatsuo, Takeuchi, Shigeo, Chiba, Hiroyuki, Ogata, Yasuhiro, Nakagoshi, Junji, Shutoh, Shin'ichi, Toba, Taturu
• Primary Examiner(s): Kriess, Kevin A.
• Assistant Examiner(s): KATBAB, ABDOLLAH
• Application Number:
  US07/853,427
• Time in Patent Office: 1,049 Days
• Field of Search: 395/700, 364/DIG. 1, 364/242.3, 364/255.1, 364/256.3, 364/256.5
• US Class Current: 719/310
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: H04L 69/00 Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass networks security protocols H04L9/40; wireless communication networks H04W

Abstract

In a parallel computer, in order to reduce the overhead of data transmissions between the processes, a data transmission from the virtual space of a process in a certain cluster to the virtual space of a process in other cluster is executed without copying the data to the buffer provided within the operating system. The real communication area resident in the real memory is provided in a part of the virtual space of the process, and an identifier unique within the cluster is given to the communication area. When the transmission process has issued a transmission instruction at the time of data transmission, the cluster address of the cluster in which the transmission destination process exists and the identifier of the communication area are determined based on the name of the transmission destination process. Then, the data is directly transmitted between the mutual real communication areas of the transmission originating process and the transmission destination process. Overhead for the data transmission between the processes can be reduced by avoiding making a copy of the data between the user space and the buffer provided within the operating system at the time of data transmission between the processes.

Claims

1. A multiple processor system, comprising:

a first cluster including at least one first processor and a first storage for holding data and a program executed by said first processor, said first cluster executing at least one first process under control of a first operating system of said first cluster, said first process being assigned with a first virtual address space;

a second cluster including at least one second processor and a second storage for holding data and a program executed by said second processor, said second cluster executing at least one second process under control of a second operating system of said second cluster, said second process being assigned with a second virtual address space which includes a virtual communication area for data transferred from other clusters including said first cluster, said second memory holding a real communication area assigned to said virtual communication area at a position of said second memory determined by said second operating system, and a base address of said real communication area written by said second operating system into said second memory, said base address indicating a top position of said real communication area within said second memory;

a network for connecting said first cluster and said second cluster;

wherein said first cluster comprises;

a send circuit connected to said first processor and said network for transmitting a packet to said second cluster by way of said network, said packet including;

(1) transmission data designated by said first process, (2) process-dependent information predetermined by said second operating system for said second process, and (3) a data offset address indicative of a difference between a base address of said virtual communication area and a virtual write address at which said transmission data is to be written within said second virtual address space; and

wherein said second cluster comprises;

a receive circuit connected to said network for receiving by way of said network, said transmission dam, said process-dependent information and said dam offset address;

a base address read circuit connected to said second memory and said receive circuit and responsive to a received said process-dependent information for generating a read address of a location within said second memory where the base address of the real communication area provided for said second process is held and for reading said base address from the location;

an address adder connected to said receive circuit and said read circuit for adding a received said data offset address to a read out said base address to generate a real address of a location within said real communication area at which said transmission data is to be written; and

a write circuit connected to said second memory and said address adder for writing, received said transmission dam at a generated said real address of said second memory.

2. A system as claimed in claim 1, wherein received said process-dependent information is a communication area identifier assigned to said real communication area for said second process.

3. A system as claimed in claim 2,

wherein said second memory holds a communication area table which includes a plurality of base addresses, each for one of a plurality of real communication areas held in said second memory, said real communication areas being allocated to a plurality of virtual communication areas belonging to virtual spaces assigned to a plurality of processes being executed by said second cluster;

and

wherein said base address read circuit generates an address of a location within said communication area table where the base address of said real communication area provided for said second process is held, in response to a received said communication area identifier.

4. A system as claimed in claim 3,

wherein said base address read circuit comprises;

a register for holding an origin address of said communication area table held in said second memory;

an offset calculation circuit for calculating an offset address indicative of a difference between a top position of said communication area table and a position within said communication area table where the base address of said real communication area provided for said second process is held, based upon a received said communication area identifier; and

an adder adding a calculated said offset address to said origin address held in said register.

5. A system as claimed in claim 3,

wherein said send circuit further transfers by way of said network, a length of said transmission data so that said length is received by said receive circuit;

wherein said communication area table further includes a plurality of lengths of said plurality of real communication areas;

wherein said base address read circuit further reads one of the plurality of lengths which is a length of said real communication area provided for said second process; and

wherein said second cluster further comprises;

a judge circuit for judging if a sum of a received said length of said transmission data and a received said data offset address is greater than a read length of said real communication area, and for prohibiting said write circuit from writing received said transmission data into said second memory, when the sum has been determined as being greater than the read length.

6. A system as claimed in claim 1;

wherein said send circuit further transmits a flag offset address by way of said network to said second cluster so that said flag offset address is received by said receive circuit, said flag offset address indicating a difference between the base address of the virtual communication area and a virtual write address at which a data receipt flag is to be written within said second virtual address space and being predetermined for said virtual write address;

wherein said address adder further adds a received said flag offset address to a read out said base address to generate a real write address of a location within said real communication area at which a data receipt flag is to be written; and

wherein said write circuit further generates a data receipt flag and writes said data receipt flag at a generated said real write address of said second memory.

7. An inter-process data transmission method in a multiple processor system which includes first and second clusters, and a network for connecting said first and second clusters, said first cluster including at least one first processor and a first storage for holding data and a program to be executed by said first processor and executing at least one first process under control of a first operating system of said first cluster, said first process being assigned with a first virtual address space which includes a first virtual communication area, said second cluster including at least one second processor and a second storage for holding data and a program to be executed by said second processor and executing at least one second process under control of a second operating system of said second cluster, said second process being assigned with a virtual address space which includes a virtual communication area,

said method comprising the steps of:

allocating, using said first operating system, an area provided within said first memory at a location determined by said first operating system to said first virtual communication area as a real communication area for said first process;

allocating, using said second operating system, an area provided within said second memory at a location determined by said second operating system to said second virtual communication area as a real communication area for said second process;

writing, using said first process, transmission data within said first virtual communication area, thereby writing said transmission data into said real communication area for said first process;

designating, using said first process;

(1) a name of said second process as a name of a destination process, (2) a virtual data read address of said first virtual space from which transmission data is to be read, (3) a length of said transmission data, and (4) a virtual data write address within said second virtual space at which said transmission data is to be written;

supplying, using said first cluster, a cluster number predetermined for said second cluster and an identifier predetermined for said real communication area provided for said second process, in response to said designated name of said second process;

calculating, using said first cluster, a data offset address indicative of a difference between a base address predetermined for second virtual communication area assigned to said second process and said virtual data write address designated by said first process;

translating, using said first cluster, said designated virtual dam read address into a real data read address for said first memory, by means of an address translation table provided by said first operating system in said first memory;

reading, using said first cluster, said transmission data from said first memory, based upon said generated real data read address and a designated said length of said transmission data;

generating, using said first cluster, a packet including;

(1) the selected cluster number of said second cluster. (2) the selected identifier of said real communication area provided for said second process, (3) a calculated said data offset address, and (4) said transmission data as read out;

sending, from said first cluster, said packet to said network;

receiving, at said second cluster, by way of said network, said identifier,

said data offset address and said transmission data included in said packet;

generating, using said second cluster, an address of a location of said second memory at which the base address of the real communication area provided for said second process is held, in response to a received said identifier;

adding, using said second cluster, a received said data offset address to a selected said base address to generate a real data write address of one location within said real communication area at which said transmission data is to be written; and

writing, using said second cluster, received said transmission data at a generated said real data write address of said second memory, based upon a received length.

8. A method as claimed in claim 7, further comprising the steps of:

writing, using said first operating system, relocation information for processes being executed by clusters other than said first cluster into said first memory, said relocation information including;

(1) a process name of each of said processes, (2) a cluster number of one of said other clusters which is executing said each process, and (3) an identifier of a real communication area provided for said each process;

writing, using said second operating system, communication information for processes being executed by said second cluster into said second memory, said communication information including;

(1) an identifier of a real communication area provided for each of said processes, and (2) a base address of said real communication area for said each process, the base address indicating a top position of said real communication area for said each process within said second memory;

wherein said supplying step executed by said first cluster includes substeps of reading said cluster number of said second cluster and said identifier of said real communication are provided for said second process from said relocation information held in said first memory, in response to a designated said name of said second process,

wherein said generating step executed by said second cluster includes substeps of reading out the base address of the second real communication area from said communication information held in said second memory.

9. A method as claimed in claim 8, further comprising the steps of:

generating, using said first cluster, a communication request after said translating step executed using said first cluster, which is before said reading step executed using said first cluster, said communication request including;

(1) a supplied said cluster number of said second cluster (2) a supplied said identifier of said real communication area for said second process, (3) a calculated said dam offset address, (4) said length of said transmission dam as designated by said first process and (5) said real dam read address as obtained by the translating step;

wherein said reading step of said transmission data is carried out based upon said real data read address included in a generated said communication request;

wherein said generating step of the communication request makes use of (1) a selected said cluster number of said second cluster (2) a selected said identifier of said real communication area for said second process, and (3) said length of said transmission data all included in a generated said communication request; and

wherein said reading step of said transmission data is carried out based upon said real data read address included in the generated said communication request.

10. A method as claimed in claim 9,

wherein said designating step includes a step of calling, using said first process, a data transmission library with an argument, said argument including:

(1) a name of said second process as a name of a destination process, (2) a virtual read address of said first virtual space from which transmission data is to be read, (3) a length of said transmission data, and (4) a virtual write address within said second virtual space at which said transmission data is to be written;

wherein said supplying step, said calculating step, said translating step and said generating step of said communication request are executed by said data transmission library; and

wherein said reading step of said transmission data is executed by a send data read circuit provided in said first cluster.

11. A method as claimed in claim 10, further comprising the steps of:

writing, using said library, a generated said communication request into said first memory; and

reading, using said send dam read circuit, said communication request from said first memory before reading said transmission data from said memory.

12. A method as claimed in claim 9,

wherein said designating step includes a step of providing, using said first process, a data transmission system call to said first operating system with an argument, said argument including:

(1) a name of said second process as a name of a destination process, (2) a virtual read address of said first virtual space from which transmission data is to be read, (3) a length of said transmission data, and (4) a virtual write address within said second virtual space at which said transmission data is to be written;

wherein said selecting step, said calculating step, said translating step and said generating step of the communication request are executed by said first operating system; and

wherein said reading step is executing by a send data read circuit provided in said first cluster.

13. A method as claimed in claim 12, further comprising the step of:

supplying, using said first operating system, said generated communication request to said send data read circuit; and

wherein said send data read circuit reads said transmission data from said first memory in response to said real read address included in a supplied said communication request.

14. A method as claimed in claim 7, further comprising the steps of:

designating, using said first process, a virtual flag write address within said second virtual space at which a data receipt flag is to be written;

calculating, using said first cluster, a flag offset address indicative of a difference between the base address predetermined for said second virtual communication area and said virtual flag write address designated by said first process;

generating, using said first cluster, said packet so that said packet includes said calculated flag offset address so that said flag offset address is received by said second cluster;

adding, using said second cluster, a received said flag offset address to a selected said base address to generate a real flag write address of another location within said real communication area at which a dam receipt flag is to be written;

writing, using said second cluster, a data receipt flag at a generated said real flag write address of said second memory;

repeatedly reading, using said second process, said another location within said second memory to detect if a data receipt flag has been written into said another location; and

reading, using said second process, said transmission data from said one location within said second memory after it has been detected that the data receipt flag has been written into said another location.

15. A multiple processor system, comprising:

a first cluster including at least one first processor and a first storage for holding data and a program executed by said first processor and executing at least one first process under control of a first operation system of said first cluster, said first process being assigned with a first virtual address space,

a second cluster including at least one second processor and a second storage for holding data and a program executed by said second processor and executing at least one second process under control of a second operating system of said second cluster, said second process being assigned with a second virtual address space;

a network for connecting said first cluster and said second cluster;

said first cluster comprising;

a send circuit connected to said first processor and said network for transmitting a packet to said second cluster by way of said network, said packet including;

(1) transmission data designated by said first process, (2) a virtual write address designated by said first process as an address of a location at which said transmission data is to be written within said second virtual space, and (3) an origin address of a page table used for address translation of the virtual write address; and

said second cluster comprising;

a receive circuit connected to said network for receiving by way of said network, said transmission data, said virtual write address and said origin address;

an address translation circuit connected to said second memory and said receive circuit and responsive to a received said original address for reading the page table held in said second memory and for translating a received said virtual write address into a real write address;

a write circuit connected to said second memory and said address translation circuit for writing a received said transmission data at a generated said real write address of said second memory.

16. A multiple processor system, comprising:

a first cluster including at least one first processor and a first storage for holding data and a program executed by said first processor and executing at least one first process under control of a first operating system of said first cluster, said first process being assigned with a first virtual address space;

a second cluster including at least one second processor and a second storage for holding data and a program executed by said second processor, and executing at least one second process under control of a second operating system of said second cluster, said second process being assigned with a second virtual address space;

a network for connecting said first and second clusters;

said first cluster including;

a path table provided by said first operating system and held in said first memory, said path table having cluster numbers of other clusters;

a cluster number read circuit responsive to a send instruction issued by said first process for reading a cluster number of said second cluster in response to path relation information designated by said send instruction which requires transfer of transmission data to said second process;

a data read circuit responsive to a virtual data read address designated by said send instruction for reading transmission data from said first memory;

an address translation circuit responsive to said path selection information designated by said send instruction for translating a virtual data write address designated by said send instruction into a real data write address of said second memory at which transmission data is to be written; and

a send circuit for transferring a packet to said network, said packet including a read said read cluster number, said transmission data and said real data write address;

said second cluster including;

a packet receive circuit connected to said network for receiving said packet; and

a data write circuit for writing said transmission dam included in a received said packet at a location having said real data write address within said second memory.