Method and apparatus for associating the reception of reset pulses by a microprocessor with access to different subprograms

• US 5,386,576 A
• Filed: 04/19/1993
• Issued: 01/31/1995
• Est. Priority Date: 01/12/1990
• Status: Expired due to Fees

• Current Assignee: Valeo Neiman
• Original Assignee: Valeo Neiman
• Inventors: Sague, Alain, Chelard, Gilles
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/049,051
• Time in Patent Office: 652 Days
• Field of Search: 395/750, 395/725, 395/700, 395/575, 371/66, 371/12, 364/707, 364/261.6, 364/261.8, 364/261.5, 364/280.2, 364/280.3, 364/DIG. 1, 364/938.1, 364/975.2, 364/DIG. 2
• US Class Current: 713/1
• CPC Class Codes: G06F 1/24 Resetting means

Abstract

A method of associating the reception of a reset pulse by a microprocessor with access to a specific subprogram depending on whether the reset pulse is associated with a system incorporating the microprocessor being switched on for the purposes of "waking up" the microprocessor, or whether it constitutes a request coming from some other unit in the system, the method being wherein it comprises the following steps: on switch-on, causing a logical data item accessible by the microprocessor to change from a first state to a second state only after a certain time interval has elapsed since the switch-on; on each occasion that a reset pulse is received, reading the logical data item before the time interval has elapsed; and depending on whether the logical data item is in its first state or in its second state, branching either to an initialization subprogram appropriate to switch-on, or else to a subprogram appropriate to processing the request.

Claims

1. In a system including a microprocessor and other units, the system applying to the microprocessor a reset pulse of a first type to for waking-up said microprocessor on switching-on, and one of said other units being capable, after switching-on, to apply to the microprocessor a reset pulse of a second type constituting a request for performing a given function, a method for accessing a first subprogram or a second subprogram as a function of the type of reset pulse received by the microprocessor comprising the following steps:

providing at said microprocessor a single reset input for receiving both types of reset pulses,

after each switching-on of the system, causing a logical data item, different from said reset pulses and readable by said microprocessor, to change from a first state to a second state only after a certain time interval has elapsed since applying a most recent reset pulse,

said step of causing the logical data item to change being performed by a circuit connected to a power supply voltage source for the microprocessor and to an input/output terminal of said microprocessor different from said single reset input and adapted to apply to said terminal a signal which passes from a low logic level to a high logic level only after said certain time interval has elapsed,

each time a reset pulse is received on said single reset input, reading said logical data item before said certain time interval has elapsed since a most recently applied reset pulse, whereby, if said reset pulse is a reset pulse on switching on, the read logical data item has not yet been changed from said first to said second state, and if said reset pulse is a reset pulse for said request, the read logical data item is already in said second state subsequent to a previous switching-on of the system, and

depending on whether said logical data item is in its first state or in its second state, branching said microprocessor either to an initialization subprogram constituting said first subprogram, or else to a subprogram for processing said request and constituting said second subprogram.

2. A system including a microprocessor and other units, said system applying to the microprocessor a reset pulse of a first type for waking-up said microprocessor on switching-on, and one of said other units being capable, after switching-on, to apply to the microprocessor a reset pulse of a second type constituting a request for performing a given function, said microprocessor including a single reset input for receiving both types of reset pulses and being capable of accessing a first subprogram or a second subprogram as a function of the type of reset pulse received by said microprocessor, said system further comprising:

means for causing, after each switching-on of the system, a logical data item, different from said reset pulses and readable by said microprocessor, to change from a first state to a second state only after a certain time interval has elapsed since applying a most recent reset pulse,

means for reading said logical data item each time a reset pulse is received on said single reset input and before said certain time interval has elapsed since a most recently applied reset pulse, whereby, if said reset pulse is a reset pulse on switching on, the read logical data item has not yet been changed from said first to said second state, and if said reset pulse is a reset pulse for said request, the read logical data item is already in said second state subsequent to a previous switching-on of the system, and

means for branching said microprocessor either to an initialization subprogram constituting said first subprogram or else to a subprogram for processing said request and constituting said second subprogram depending on whether said logical data item is in its first state or in its second state, and further comprising a circuit connected to a power supply voltage source of said microprocessor and to an input/output terminal of said microprocessor different from said single reset input, and adapted to apply to said terminal a signal which passes from a low logic level to a high logic level constituting the second state of the logical data item, only after said certain time interval has elapsed,

said circuit comprising a resistor connected between the microprocessor power supply voltage source and the input/output terminal of said microprocessor, and a capacitor connected between said input/output terminal and ground.

3. A system including a microprocessor and other units, said system applying to the microprocessor a reset pulse of a first type for waking-up said microprocessor on switching-on, and one of said other units being capable, after switching-on, to apply to the microprocessor a reset pulse of a second type constituting a request for performing a given function, said microprocessor including a single reset input for receiving both types of reset pulses and being capable of accessing a first subprogram or a second subprogram as a function of the type of reset pulse received by said microprocessor, said system further comprising:

means for causing, after each switching-on of the system, a logical data item, different from said reset pulses and readable by said microprocessor, to change from a first state to a second state only after a certain time interval has elapsed since applying a most recent reset pulse,

means for reading said logical data item each time a reset pulse is received on said single reset input and before said certain time interval has elapsed since a most recently applied reset pulse, whereby, if said reset pulse is a reset pulse on switching on, the read logical data item has not yet been changed from said first to said second state, and if said reset pulse is a reset pulse for said request, the read logical data item is already in said second state subsequent to a previous switching-on of the system, and

means for branching said microprocessor either to an initialization subprogram constituting said first subprogram or else to a subprogram for processing said request and constituting said second subprogram depending on whether said logical data item is in its first state or in its second state, and further comprising a circuit connected to a power supply voltage source of the microprocessor and to an input/output terminal of said microprocessor, different from said single reset input and adapted to apply to said terminal a signal which passes from a high logic level to a low logic level constituting the second state of the logical data item, only after said certain time interval has elapsed,

said circuit comprising a capacitor connected between the microprocessor power supply voltage source and the input/output terminal of said microprocessor, and a resistor connected between said input/output terminal and ground.

4. In a system including a microprocessor and other units, the system applying to the microprocessor a reset pulse of a first type for waking-up said microprocessor on switching-on, and one of said other units being capable, after switching-on, to apply to the microprocessor a reset pulse of a second type constituting a request for performing a given function, a method for accessing a first subprogram or a second subprogram as a function of the type of reset pulse received by the microprocessor comprising the following steps:

providing at said microprocessor a single reset input for receiving both types of reset pulses,

after each switching-on of the system, causing a logical data item, different from said reset pulses and readable by said microprocessor, to change from a first state to a second state only after a certain time interval has elapsed since applying a most recent reset pulse,

said step of causing the logical data item to change being performed by a circuit connected to a power supply voltage source for the microprocessor and to an input/output terminal of said microprocessor different from said single reset input and adapted to apply to said terminal a signal which passes from a high logic level to a low logic level only after said certain time interval has elapsed,

each time a reset pulse is received on said single reset input, reading said logical data item before said certain time interval has elapsed since a most recently applied reset pulse, whereby, if said reset pulse is a reset pulse on switching on, the read logical data item has not yet been changed from said first to said second state, and if said reset pulse is a reset pulse for said request, the read logical data item is already in said second state subsequent to a previous switching-on of the system, and

depending on whether said logical data item is in its first state or in its second state, branching said microprocessor either to an initialization subprogram constituting said first subprogram, or else to a subprogram for processing said request and constituting said second subprogram.