Correction range technique for multi-range A/D converter

• US 5,387,914 A
• Filed: 02/22/1993
• Issued: 02/07/1995
• Est. Priority Date: 02/22/1993
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Mangelsdorf, Christopher W.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/020,556
• Time in Patent Office: 715 Days
• Field of Search: 341/118, 341/120, 341/156, 341/158, 341/159
• US Class Current: 341/156
• CPC Class Codes: H03M 1/069 by range overlap between successive stages or steps
• CPC Class Codes: H03M 1/165 in which two or more residues with respect to different reference levels in a stage are used as input signals for the next stage, i.e. multi-residue type

Abstract

An analog-to-digital converter (ADC) having three cascaded A/D stages of the "flash" type. In the first stage, the analog signal is compared with a set of threshold reference voltages so as to develop a set of most-significant bits and to produce two analog residue signals: (1) a normal residue corresponding to the difference between the analog input and the reference voltage next below the analog input, and (2) a second residue corresponding to the difference between the analog input and the reference voltage next above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage. The second A/D stage develops a set of less-significant bits and two more residue signals for the third A/D stage. The second stage further includes a capacitor network arranged to effectively double the operating range of that stage to accommodate error correction.

Claims

1. In a multi-stage A/D converter of the type where at least one stage comprises a flash converter producing two residue signals for the following stage;

that improvement for providing error correction capability by expanding the operating range of said following stage, comprising;

a first flash stage having output means to produce said two residue signals which together represent a least significant bit (LSB) of said first flash stage;

a second flash stage having an input receiving said residue signals;

said second flash stage having a nominal operating range for processing normal error-free input signals;

said second stage comprising a network responsive to said two residue signals and operable to produce corresponding threshold signals for a set of comparators to produce logic signals representing digitally the magnitude of the input signal defined by said two residue signals;

said network comprising means to produce threshold signals outside of said nominal range of said second stage.

2. An A/D converter as in claim 1, wherein said network comprises a plurality of interconnected impedance elements.

3. An A/D converter as in claim 2, wherein the impedance elements are capacitors.

4. An A/D converter as in claim 1, wherein said residue signals are differential in format.

5. An A/D converter as in claim 4, wherein the threshold signals from said network are differential in format.

6. An A/D converter as in claim 5, wherein at least some of said comparators have four input terminals to receive two differential signals.

7. An A/D converter as in claim 1, wherein said network comprises a plurality of resistors.

8. An A/D converter as in claim 7, wherein said network resistors are connected in series as a string;

said network further includes additional resistors at the ends of said string of resistors for establishing a correction range; and

first and second amplifiers responsive to said residue signals and having their outputs connected to said additional resistors in a negative feedback circuit arrangement.

9. A multi-stage A/D converter comprising at least three successive stages;

each of said stages including a flash converter for producing a digital flash signal responsive to the analog signal input;

at least the first and second of said flash stages including means to develop two residue signals responsive to the relative magnitude of the analog signal and the two quantization signal levels above and below the analog signal;

said two residue signals together defining one LSB of that stage; and

means associated with each of said flash stages for producing respective digital signals to be combined to produce a final composite output signal.

10. An A/D converter as in claim 9, including two inter-stage amplifiers between said successive stages to intensify said residue signals prior to application to the next stage.

11. An A/D converter as in claim 9, wherein at least one of said stages following the first stage has a nominal operating range suitable in magnitude for processing error-free signals from the preceding stage;

and

means forming part of said at least one stage for expanding operating range thereof so as to accommodate error correction.

12. An A/D converter as in claim 11, wherein said expanding means comprises a network responsive to the two residue signals from the preceding stage and producing respective nodal voltages defining threshold levels for a bank of comparators associated with the flash stage.

13. An A/D converter as in claim 12, wherein said network includes a plurality of impedance elements.

14. An A/D converter as in claim 13, wherein said impedance elements are capacitors.