Video multiplexing system for superimposition of scalable video streams upon a background video data stream

• US 5,387,945 A
• Filed: 01/24/1994
• Issued: 02/07/1995
• Est. Priority Date: 07/13/1988
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Takeuchi, Kesatoshi
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US08/185,155
• Time in Patent Office: 379 Days
• Field of Search: 348/565, 348/567, 348/718, 348/719, 348/714, 348/552, 348/581, 348/588, 348/564, 345/200
• US Class Current: 348/564
• CPC Class Codes: G09G 1/167 Details of the interface to the display terminal specific for a CRT details suitable for both CRT and flat panel G09G5/006, specific for a flat panel G09G3/2096
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/44 Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/44504 Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

A video multiplexing system for superimposition of scalable video data streams upon a background data stream has a video decoder to extract a first luminance signal, an A/D converter to convert the first luminance signal to digital form, a three-port video memory for storing the digitized luminance signal, a D/A converter for receiving the stored digitized luminance signal and converting it to analog form, a mixing, or multiplexing means, having one input coupled to the D/A converter output, at least one other luminance signal source as an input and control inputs for directing the selection of one of the input luminance signals as an output, and a control means such as a microprocessor for controlling the various components. The write operations to the video memory are synchronized to the incoming luminance signal, and the read operations from video memory are synchronized to the display device. This video multiplexing architecture provides the ability to open a viewport of arbitrary size at any position within a larger display. Scaling of the digitized luminance signal to fit an a viewport of arbitrary size is achieved by varying the frequency of the A/D converter clocks so as to expand or shrink the resulting image.

Claims

1. An apparatus for processing image signal, for use in a computer system having a CPU, a CPU bus connected to said CPU, a display controller, and a display device, comprising:

a video memory for memorizing a given digital image signal;

first write control means connected to said CPU bus, for controlling the writing of said given digital image signal in said video memory by supplying a first write address to said video memory, a range of said first write address being specified with a plurality of write address parameters set by said CPU;

a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said plurality of image signals;

first read control means, connected to said CPU bus, for supplying said video switch with a first selection signal indicating to select one of said plurality of image signals, and controlling the reading of said first image signal out of said video memory by supplying a first read address to said video memory in synchronism with a first horizontal synchronizing signal and a first vertical synchronizing signal which are supplied from said display controller, a range of said first read address being specified with a plurality of read address parameters set by said CPU;

an analog-to-digital converter for converting a given analog image signal into said given digital image signal to supply said given image signal to said video memory; and

wherein

said first write control means includes;

means for generating a first clock signal on the basis of said plurality of write address parameters and a second horizontal synchronizing signal, and supplying said first clock signal to said analog-to-digital converter, said first clock signal having a first frequency which has a value of a frequency of said second horizontal synchronizing signal multiplied by a first integer included in said plurality of write address parameters, said first clock signal regulating the timing of said converting in said analog-to-digital converter, whereby a horizontal size of a first image represented by the image signal memorized in said video memory is changeable by changing said first integer.

2. An apparatus in accordance with claim 1, wherein said first write control means further includes:

means for generating a second clock signal on a basis of a second vertical synchronizing signal, and supplying said second clock signal to said video memory, said second clock signal regulating increment of a vertical write address of said video memory, said second clock signal having a second frequency which has a value of a frequency of said second vertical synchronizing signal multiplied by a second integer included in said plurality of write address parameters, whereby a vertical size of said first image represented by said image signal memorized in said video memory is changeable by changing said second integer.

3. An apparatus in accordance with claim 2, wherein said first write control means further includes:

means for generating a write enable signal on the basis of said plurality of write address parameters, said second vertical synchronizing signal, and said second horizontal synchronizing signal, and supplying said write enable signal to said video memory, to thereby enable the writing of said given digital image signal in said video memory for a first horizontal range of said write address and for a first vertical range of said write address, said first horizontal range and said first vertical range being specified by said plurality of write address parameters.

4. An apparatus in accordance with claim 1, further comprising:

a video signal decoder, connected to said analog-to-digital converter, for decoding a given composite video signal to generate said given analog image signal, said second-horizontal synchronizing signal, and said second-vertical synchronizing signal.

5. An apparatus in accordance with claim 4, further comprising:

input means for receiving a plurality of composite video signals; and

first selection means, connected to said CPU bus, for selecting one of said plurality of composite video signals to supply said selected composite video signal to said video signal decoder, said selecting being specified by said CPU.

6. An apparatus in accordance with claim 5, wherein

said input means includes a television tuner connected to said CPU bus, a frequency to be tuned by said television tuner being specified by said CPU.

7. An apparatus for processing image signals, for use in a computer system having a CPU, a CPU bus connected to said CPU, a display controller, and a display device comprising:

a video memory for memorizing a given digital image signal

first write control means, connected to said CPU bus, for controlling the writing of said given digital image signal in said video memory by supplying a first write address to said video memory, a range of said first write address being specified with a plurality of write address parameters set by said CPU;

a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said plurality of image signals;

first read control means, connected to said CPU bus, for supplying said video switch with a first selection signal indicating to select one of said plurality of image signals, and controlling the reading of said first image signal out of said video memory by supplying a first read address to said video memory in synchronism with a first horizontal synchronizing signal and a first vertical synchronizing signal which are supplied from said display controller, a range of said first read address being specified with a plurality of read address parameters set by said CPU;

second selection means, connected to said video memory, for selecting one of a plurality of digital image signals to supply the selected digital image signal to said video memory;

address selection means, connected to said first write control means and said video memory, for selecting one of a plurality of write addresses including said first write address supplied from said first write control means; and

second write control means, connected to said CPU bus, for receiving a first image signal from said CPU through said CPU bus, supplying said first image signal as one of said plurality of digital image signals to said second selection means, supplying a second write address for said first image signal as one of said plurality of write addresses to said address selection means, supplying a second selection signal to said second selection means to instruct said selecting in said second selection means, and supplying a third selection signal to said address selection means to instruct said selecting in said address selection means.

8. An apparatus for processing image signals, for use in a computer system having a CPU, a CPU bus connected to said CPU, a display controller, and a display device, comprising:

a video memory for memorizing a given digital image signal;

first write control means, connected to said CPU bus, for controlling the writing of said given digital image signal in said video memory by supplying a first write address to said video memory, a range of said first write address being specified with a plurality of write address parameters set by said CPU;

a video switch for receiving a plurality of image signals including a first image signal read out of said video memory, and selecting one of said Plurality of image signals; and

first read control means, connected to said CPU bus, for supplying said video switch with a first selection signal indicating to select one of said plurality of image signals, and controlling the reading of said first image signal out of said video memory by supplying a first read address to said video memory in synchronism with a first horizontal synchronizing signal and a first vertical synchronizing signal which are supplied from said display controller, a range of said first read address being specified with a plurality of read address parameters set by said CPU.

wherein said first read control means includes;

means for generating a first clock signal on the basis of said plurality of read address parameters and said first horizontal synchronizing signal, and supplying said first clock signal to said video memory, said first clock signal regulating increment of a horizontal read address of said video memory, said clock signal having a frequency which has a value of a frequency of said first horizontal synchronizing signal multiplied by a first integer included in said plurality of read address parameters, whereby a horizontal size of a second image represented by said first image signal read out from said video memory is changeable by changing said third integer.

9. An apparatus in accordance with claim 8, wherein said first read control means further includes:

means for generating a second clock signal on the basis of said first vertical synchronizing signal, and supplying said second clock signal to said video memory, said second clock signal regulating increment of a vertical read address of said video memory, said second clock signal having a second frequency which has a value of a frequency of said first vertical synchronizing signal multiplied by a second integer included in said plurality of read address parameters, whereby a vertical size of said second image represented by said first image signal is changeable by changing said second integer.

10. An apparatus in accordance with claim 9, wherein said first read control means further includes:

means for generating a read enable signal on the basis of said plurality of read address parameters, said first horizontal synchronizing signal, and said first vertical synchronizing signal, and supplying said read enable signal to said video memory, to thereby enable the reading of said first image signal from said video memory for a second horizontal range of said read address and for a second vertical range of said read address, said second horizontal range and said second vertical range being specified by said plurality of read address parameters.

11. An apparatus in accordance with claim 10, wherein said first read control means further includes:

means for supplying said read enable signal as said first selection signal to said video switch to select said first image signal read out of said video memory for said second horizontal range and said second vertical range of said read address.

12. An apparatus in accordance with claim 11, wherein

said plurality of image signals supplied to said video switch includes said first image signal read out of said video memory and a basic image signal supplied from said display controller;

and

said video switch selects to output said first image signal for said second horizontal range and said second vertical range of said read address, and selects to output said basic image signal for a range other than said second horizontal range and said second vertical range of said read address, whereby said second image reproduced by said first image signal is displayed in an area specified by said plurality of read address parameters within a basic image reproduced by said basic image signal on said display device.

13. An apparatus in accordance with claim 12, wherein said first read control means further includes:

means for generating a third clock signal corresponding a horizontal dot clock signal used in said display device, said third clock having a third frequency which has a value of a frequency of said first horizontal synchronizing signal multiplied by a predetermined third integer; and

means, in response to said read enable signal, for selectively supplying said first clock signal to said video memory for said second horizontal range and said second vertical range of said read address, and supplying said third clock signal to said video memory for a range of said read address other than said second horizontal range and said second vertical range.

14. An apparatus in accordance with claim 8, further comprising:

a digital-to-analog converter, connected between said video memory and said video switch, for converting said first image signal read out of said video memory in the form of a digital signal into a first analog image signal, and supplying said first analog image signal to said video switch; and

means for supplying said third clock signal to said digital-to-analog converter to regulate the timing of said converting in said digital-to-analog converter.

15. An apparatus in accordance with claim 12, further comprising:

superimposing means for generation a superimpose-enable signal as a function of said basic image signal, said superimpose-enable signal indicating that a part of said basic image is superimposed in said second image displayed on said displayed device; and

a logic circuit for executing a logic operation on said read enable signal and said superimpose-enable signal to generate said first selection signal.

16. An apparatus in accordance with claim 15, wherein said superimposing means includes:

a comparator for comparing said basic image signal with a predetermined reference value to generate said superimpose-enable signal.