Reconfigurable programmable digital filter architecture useful in communication receiver
First Claim
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1. In a reconfigurable programmable digital filter structure suitable for use as a deghosting filter;
- wherein said structure includes first and second input-weighted digital filter means each of which has a given number of multiplier-coefficient taps;
a combination comprising;
input means for providing input signals to said digital filter means;
filter-reconfiguration means including multiplexer means coupled to said digital filter means (1) for configuring said first and second digital filter means for operation as a single complex digital filter means with said given number of complex multiplier coefficients for a complex sampled input signal provided thereto by said input means, or (2) for configuring at least one of said first and second digital filter units for operation as a separate real digital filter means with twice said given number of real multiplier coefficients for a real sampled input signal provided thereto by said input means; and
output means for receiving output signals from said digital filter means.
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Abstract
A VLSI integrated circuit, which comprises a single IIR input and global section and identically-structured cascadable filter sections, each of which filter sections includes a pair of time-multiplexed, real-coefficient, input-weighted FIR filter units and additional delay means, can be selectively programmed to operate in any one of a number of different filter configurations that can define real FIR or IIR filters, complex FIR or IIR filters, or filters which are various combinations thereof. One or more of such integrated circuits are useful for implementing a digital deghosting and/or equalization filter.
139 Citations
17 Claims
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1. In a reconfigurable programmable digital filter structure suitable for use as a deghosting filter;
- wherein said structure includes first and second input-weighted digital filter means each of which has a given number of multiplier-coefficient taps;
a combination comprising;input means for providing input signals to said digital filter means; filter-reconfiguration means including multiplexer means coupled to said digital filter means (1) for configuring said first and second digital filter means for operation as a single complex digital filter means with said given number of complex multiplier coefficients for a complex sampled input signal provided thereto by said input means, or (2) for configuring at least one of said first and second digital filter units for operation as a separate real digital filter means with twice said given number of real multiplier coefficients for a real sampled input signal provided thereto by said input means; and output means for receiving output signals from said digital filter means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- wherein said structure includes first and second input-weighted digital filter means each of which has a given number of multiplier-coefficient taps;
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14. A VLSI chip having a given chip structure for defining a reconfigurable programmable digital filter for a periodically sampled input signal;
- wherein each sample period is divided into two successive clock periods; and
wherein said given chip structure comprises a first given plural number of filter substructures and a single IIR input and global substructure; and
wherein;each of said filter sub-structures includes a pair of first and second input-weighted digital filter means that each comprise (a) a second given plural number of taps, (b) two multiplier-accumulator registers between taps thereof and (c) first programmable delay means between taps thereof for introducing a sample delay that can be adjusted between first and second relatively small numbers of sample periods, means comprising programmable multiplexer means coupled to said digital filter means
1) for configuring each pair of first and second digital filter means as a single complex digital filter means with said second given plural number of complex multiplier coefficients for a complex sampled input signal applied thereto, or (2) for configuring at least one of said first and second digital filter means as a separate real digital filter unit with twice said second given plural number of real multiplier coefficients for a real sampled input signal applied thereto, and second programmable delay means for introducing a sample delay that can be adjusted between one clock period and a relatively large numbers of sample periods; andsaid single IIR input and global sub-structure includes in-phase and quadrature-phase means for programmably adjusting the phase of samples applied as inputs thereto, and programmable routing multiplexers (1) for selectively applying the output of a certain one of said filter sub-structures as inputs to said in-phase and quadrature-phase means, and (2) for selectively cascading at least some of said first given plural number of filter sub-structures to alternatively configure said cascaded filter sub-structures as a certain real FIR or IIR filter, complex FIR or IIR filter, or a particular combination of real and complex FIR and/or IIR filters. - View Dependent Claims (15, 16, 17)
- wherein each sample period is divided into two successive clock periods; and
Specification