Filter circuit with switchable finite impulse response and infinite impulse response filter characteristics

• US 5,388,063 A
• Filed: 11/18/1993
• Issued: 02/07/1995
• Est. Priority Date: 11/18/1992
• Status: Expired due to Fees

• Current Assignee: YOZAN, Inc.
• Original Assignee: YOZAN, Inc.
• Inventors: Yamamoto, Makoto, Takatori, Sunao
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US08/154,036
• Time in Patent Office: 446 Days
• Field of Search: 364/724.17, 364/724.13, 364/724.01, 364/825
• US Class Current: 708/320
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters

Abstract

A filter which can operate as a digital filter of the finite impulse response type or the infinite impulse response type using one circuit. The signal to be filtered is multiplied and added using a first calculation circuit and a second calculation circuit. The outputs of the calculation circuits are added using addition circuits. Either the output of the addition circuit or the input of the first calculation circuit is applied by a switching element to the first calculation circuit.

Claims

1. A filter circuit comprising:

i) first circuit means having a plurality of first holding circuits and a plurality of first multiplication circuits, said first holding circuits for holding first input data in time series and each of said first multiplication circuits for multiplying an output of one of said first holding circuits by a first mutiplier;

ii) second circuit means having a plurality of second holding circuits and a plurality of second multiplication circuits, said second holding circuits for holding second input data and each of said second multiplication circuits for multiplying an output of one of said second holding circuits by a second multiplier;

iii) addition means for calculating a total summation of multiplication results of said first and second circuit means; and

iv) a switching circuit for inputting either an output of said addition circuit or delayed first input data as the second input data to said second circuit means.

2. A filter circuit as recited in claim 1, wherein said addition means is comprised of one addition circuit which receives outputs from all the first and second multiplication circuits.

3. A filter circuit as recited in claim 1, wherein said addition means comprises a plurality of first addition circuits and a second addition circuit, each said first addition circuit having two input terminals for receiving one multiplication result and one addition result, said second addition circuit having three input terminals for receiving one multiplication result and two addition results.

4. A filter circuit as recited in claim 1, wherein said addition means include a plurality of parallel-connected capacitors, each receiving a multiplication result or an addition result at one end, and each being connected at the other end.

5. A filter circuit as recited in claim 1, wherein at least one of a group of said first holding circuits and said second holding circuits is comprised of:

a first amplifier receiving said first input data;

a first transistor having a gate coupled with a first clock, a drain coupled with an output of said first amplifier, and a source coupled with an input of said first amplifier;

a first capacitor coupled with said source of said first transistor and ground;

a second amplifier having an input coupled with said source of said first transistor;

a second transistor having a gate coupled with a second clock, a drain coupled with an output of said second amplifier, and a source coupled with an input of said second amplifier, said second clock and said first clock are out of phase; and

a second capacitor coupled with said source of said second transistor and ground, where

said second amplifier outputs delayed first input data which is based on said first input data.

6. A filter circuit as recited in claim 1, wherein at least one of a group of said first multiplication circuits and said second multiplication circuits is comprised of:

a clock and for generating clocking signals;

an inverter for inverting said clocking signals to generate inverted clocking signals;

a first amplifier receiving input data at a first input;

a first transistor having a gate coupled with said clocking signal, a source coupled with an output of said first amplifier and a drain;

a first capacitor coupled with said drain of said first transistor;

a second capacitor coupled with said first capacitor and ground, where a potential difference between said first and said second capacitor is input to a second input of said first transistor;

an output capacitor coupled with said drain of said first transistor and said first capacitor;

a second amplifier having a first input coupled with ground and a second input coupled with said output capacitor, said drain of said first transistor and said first capacitor; and

a second transistor having a gate coupled with said inverted clocking signal, a source coupled with an output of said second amplifier, and a drain coupled with said second input of said second amplifier.

7. A filter circuit claimed in claim 1, wherein a finite impulse response characteristic is realized when said switching circuit inputs said delayed first input data as second input data.

8. A filter circuit claimed in claim 1, wherein an infinite impulse response characteristic is realized when said switching circuit inputs said addition circuit output as second input data.

9. A method for generating finite impulse response characteristics and infinite impulse response characteristics using one circuit, said method including the steps of:

holding at least one first input data in time series;

multiplying each said first input data by a first multiplier to generate multiplied first input data;

holding at least one second input data;

multiplying each said second input data by a second multiplier to generate multiplied second input data;

calculating a total summation of said multiplied first input data and said multiplied second input data; and

inputting said total summation or delayed first input data as second input data.

10. A method as recited by claim 9, wherein all multiplied first input data and all multiplied second input data are summed to calculate said total summation in one addition circuit.

11. A method as recited by claim 9, wherein the step of calculating said total summation includes the steps of:

sequentially summing all multiplied first input data;

sequentially summing all multiplied second input data; and

summing said sequential sum of said first input data and said sequential sum of said second input data.

12. A method as recited by claim 11, wherein said total summation is calculated by inputting said multiplied first input data and said multiplied second input data into a plurality of parallel-connected capacitors which have commonly connected outputs.

13. A method as recited in claim 9, wherein the step of holding first input data includes the following steps:

inputting first input data to a drain of a first transistor;

triggering said first transistor to conduct using a first clock so that first transistor source is equal to said first input data;

storing said first input data from said first transistor source in a first capacitor;

inputting said stored first input data from said capacitor to a drain of a second transistor;

triggering said second transistor to conduct using a second clock so that a second transistor source is equal to said first input data from said second transistor drain, said second clock being out of phase with said first clock; and

storing said first data from said second transistor source in a second capacitor, where

said output data is delayed and based on said first input data.

14. A method as recited in claim 9, wherein one of said steps of multiplying includes the steps of:

inputting data to be multiplied to a transistor assembly;

triggering said transistor assembly with a digital signal so that said transistor assembly conducts said input data;

storing said conducted input signal, said stored signal being used as output in a capacitor;

inverting said digital signal;

triggering a second transistor assembly with said inverted digital signal; and

grounding said output when said second transistor is triggered.

15. A method as recited in claim 9, wherein a finite impulse response characteristic is realized when said delayed first input data is used as second data.

16. A method as recited in claim 9, wherein an infinite impulse response characteristic is realized when said total summation is used as second data.