Semiconductor integrated circuit
First Claim
1. A semiconductor integrated circuit comprising:
- a first data line;
a second data line;
a match line;
a control word line;
first connection means for controllably electrically connecting the control word line to the match line;
potential float means for controllably allowing a potential of the control word line to float; and
a memory cell, comprising;
second connection means for providing a circuit path between the match line and one of the first data line and the second data line, andenable means for selectively enabling the circuit path;
wherein the potential float means and the first connection means are enabled during a data retrieval operation to allow the potential of the control word line to positively correlate to an electric potential of the match line.
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Accused Products
Abstract
A semiconductor integrated circuit is a CAM memory which comprises at least one memory cell including a first storage unit for defining the electrical connection and otherwise the non-connection between a first data line and a match line and a second storage unit for defining the electrical non-connection and otherwise the connection between a second data line and the match line, and a control word line for controlling said first and second storage units in the memory cell, the match line corresponding to at least one of the control word lines, the control word line being used to effect the connection and otherwise non-connection between each of said first and second data lines and the match line in accordance with the definition of connections of said first and second storage units. Moreover, the storage unit can be composed of a coupler of a nonvolatile memory element such as a MONOS-type nonvolatile memory element, PROM, EPROM EEPROM, UVEPROM and a like, and the memory cell further may include at least one selective transistor. The CAM memory comprises at least one of potential detecting means of defecting an electric potential of the match line, holding means for holding the result of detection in response to each control word line and preventing means for preventing the through current between the memory cells in conformity with and in nonconformity with the retrieval data.
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Citations
77 Claims
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1. A semiconductor integrated circuit comprising:
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a first data line; a second data line; a match line; a control word line; first connection means for controllably electrically connecting the control word line to the match line; potential float means for controllably allowing a potential of the control word line to float; and a memory cell, comprising; second connection means for providing a circuit path between the match line and one of the first data line and the second data line, and enable means for selectively enabling the circuit path; wherein the potential float means and the first connection means are enabled during a data retrieval operation to allow the potential of the control word line to positively correlate to an electric potential of the match line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor integrated circuit comprising:
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a plurality of retrieval memory word cells, the plurality of cells arranged in a rectangular matrix array, the array having a plurality of rows of cells and a plurality of columns of cells; a plurality of control word lines, each control word line associated with a corresponding row of cells; a plurality of match lines, each match line associated with a corresponding plurality of rows of cells; a plurality of first data lines, each first data line associated with a corresponding column of cells; a plurality of second data lines, each second data line associated with a corresponding of column of cells; and a plurality of potential detecting means for detecting an electrical potential of a match line, each potential detecting means connected to a corresponding match line; wherein each retrieval memory word cell comprises; connection means for providing a circuit path between the corresponding match line and one of the corresponding first and second data lines, and enable means for controllably enabling the circuit path; and wherein the corresponding control word line operates the enable means of each of the memory cells of the corresponding row during a data retrieval operation to electrically connect the corresponding match line to various ones of the plurality of first and second data lines. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A semiconductor integrated circuit, comprising:
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a match line; a first data line; a second data line; a memory cell, comprising; connection means for selectively providing a circuit path between the match line and one of the first and second data lines, and enable means for controllably enabling the circuit path; a control word line controlling the connection means; and a control line controlling the enable means; wherein the control word line and control line control the connection means and enable means to connect the match line to one of the first and second data lines during a data retrieval operation. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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43. A semiconductor integrated circuit, comprising:
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a plurality of retrieval memory cells, the plurality of cells arranged in a rectangular matrix array, the array having a plurality of rows of cells and a plurality of columns of cells; a plurality of control word lines, each control word line associated with a corresponding row of cells; a plurality of match lines, each match line associated with a corresponding plurality of rows of cells; a plurality of sets of first and second data lines, each set associated with a corresponding column of cells; and a plurality of potential detecting means, each potential detecting means connected to a corresponding match line; wherein each memory cell comprises; connection means for selectively providing a circuit path between the corresponding match line and one of the first and second data lines of the corresponding set of first and second data lines, enable means for controllably enabling the circuit path, and a control line controlling the enable means, wherein the corresponding control word line controls the connection means; and wherein the corresponding control word line and control line control the connection means of each cell of the corresponding row to establish the circuit paths between the sets of first and second data lines and the corresponding match line during a data retrieval operation. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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60. A semiconductor integrated circuit, comprising:
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a first transistor chain comprising a plurality of serially connected transistors; a second transistor chain comprising a plurality of serially connected transistors; a first data line connected to a first end of the first transistor chain; a second data line connected to a first end of the second transistor chain; a match line; potential detecting means for detecting an electrical potential of the match line; and a selective transistor connecting the match line to second ends of each of the first and second transistor chains. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
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76. A semiconductor integrated circuit comprising:
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a transistor; a first signal line connected to one of a source electrode of the transistor and a drain electrode of the transistor; a second signal line connected to the other of the source and drain electrodes; a control word line connected to a gate of the transistor; connection means for controllably electrically connecting the first signal line to the control word line; and potential float means for allowing an electrical potential of the control word line to float; wherein the transistor operates as a unidirectional element between the first signal line and the second signal line when the connection means and potential float means are activated.
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77. A semiconductor integrated circuit comprising:
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a memory cell; a match line; a control word line; a first data line; a second data line; potential float means for allowing a potential of the control word line to float; connection means for electrically connecting the control word line to the match line; and control means for operating the potential float means and the connection means during a data retrieval operation so that the potential of the control word line positively correlates to a potential of the match line; wherein the memory cell comprises a first storage means for providing a first circuit path between the match line and the first data line; second storage means for providing a second circuit path between the match line and the second data line; and enable means for controllably enabling one of the first and second circuit paths; and wherein the potential float means and the first connection means are enabled during a data retrieval operation to allow the potential of the control word line to positively correlate to a potential of the match line.
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Specification