Semiconductor integrated circuit

• US 5,388,065 A
• Filed: 05/14/1992
• Issued: 02/07/1995
• Est. Priority Date: 05/16/1991
• Status: Expired due to Term

• Current Assignee: Kawasaki Microelectronics Incorporated (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Yoneda, Masato
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US07/883,595
• Time in Patent Office: 999 Days
• Field of Search: 365/49, 365/190, 365/189.01, 365/154, 365/182, 365/185
• US Class Current: 365/49.17
• CPC Class Codes: G11C 15/046 using non-volatile storage elements

Abstract

A semiconductor integrated circuit is a CAM memory which comprises at least one memory cell including a first storage unit for defining the electrical connection and otherwise the non-connection between a first data line and a match line and a second storage unit for defining the electrical non-connection and otherwise the connection between a second data line and the match line, and a control word line for controlling said first and second storage units in the memory cell, the match line corresponding to at least one of the control word lines, the control word line being used to effect the connection and otherwise non-connection between each of said first and second data lines and the match line in accordance with the definition of connections of said first and second storage units. Moreover, the storage unit can be composed of a coupler of a nonvolatile memory element such as a MONOS-type nonvolatile memory element, PROM, EPROM EEPROM, UVEPROM and a like, and the memory cell further may include at least one selective transistor. The CAM memory comprises at least one of potential detecting means of defecting an electric potential of the match line, holding means for holding the result of detection in response to each control word line and preventing means for preventing the through current between the memory cells in conformity with and in nonconformity with the retrieval data.

Claims

1. A semiconductor integrated circuit comprising:

a first data line;

a second data line;

a match line;

a control word line;

first connection means for controllably electrically connecting the control word line to the match line;

potential float means for controllably allowing a potential of the control word line to float; and

a memory cell, comprising;

second connection means for providing a circuit path between the match line and one of the first data line and the second data line, and

enable means for selectively enabling the circuit path;

wherein the potential float means and the first connection means are enabled during a data retrieval operation to allow the potential of the control word line to positively correlate to an electric potential of the match line.

2. The semiconductor integrated circuit of claim 1, wherein said match line further has potential detecting means for detecting the electric potential of said match line.

3. The semiconductor integrated circuit of claim 1, wherein said match line further has fixing means for fixing the electric potential of said match line.

4. The semiconductor integrated circuit of claim 1, wherein the second connection means comprises a first storage unit providing a first circuit path between the match line and the first data line and a second storage unit providing a second circuit path between the match line and the second data line.

5. The semiconductor integrated circuit of claim 4, wherein said first and second storage units each comprise a coupler.

6. The semiconductor integrated circuit of claim 4, wherein each of said first and second storage units comprises a nonvolatile memory element, each nonvolatile memory element connected to the enable means.

7. The semiconductor integrated circuit of claim 4, wherein said first and second storage units each comprise a nonvolatile memory element.

8. The semiconductor integrated circuit of claim 7, wherein said nonvolatile memory element is a MONOS-type nonvolatile memory element.

9. The semiconductor integrated circuit of claim 1, wherein the enable means is a selective transistor.

10. The semiconductor integrated circuit of claim 9, wherein said selective transistor is a unidirectional element.

11. The semiconductor integrated circuit of claim 10, wherein said unidirectional element has a threshold voltage higher than that of any peripheral element.

12. A semiconductor integrated circuit comprising:

a plurality of retrieval memory word cells, the plurality of cells arranged in a rectangular matrix array, the array having a plurality of rows of cells and a plurality of columns of cells;

a plurality of control word lines, each control word line associated with a corresponding row of cells;

a plurality of match lines, each match line associated with a corresponding plurality of rows of cells;

a plurality of first data lines, each first data line associated with a corresponding column of cells;

a plurality of second data lines, each second data line associated with a corresponding of column of cells; and

a plurality of potential detecting means for detecting an electrical potential of a match line, each potential detecting means connected to a corresponding match line;

wherein each retrieval memory word cell comprises;

connection means for providing a circuit path between the corresponding match line and one of the corresponding first and second data lines, and

enable means for controllably enabling the circuit path; and

wherein the corresponding control word line operates the enable means of each of the memory cells of the corresponding row during a data retrieval operation to electrically connect the corresponding match line to various ones of the plurality of first and second data lines.

13. The semiconductor integrated circuit of claim 12 wherein each of said first and second storage units comprises a nonvolatile memory element, each nonvolatile memory element connected to the enable means.

14. The semiconductor integrated circuit of claim 12, wherein said match line further has fixing means for fixing the electric potential of said match line.

15. The semiconductor integrated circuit of claim 12, further comprising a plurality of potential float means, each potential float means for allowing a potential of a corresponding control word line to float and a plurality of second connection means, each connection means for connecting a corresponding control word line to the corresponding match line, said plurality of connection means and said plurality of potential float means being activated during the data retrieval operation, the electric potential of said match line becoming positively correlated to the potential of said control word line.

16. The semiconductor integrated circuit of claim 12, further comprising holding means for holding the result of a detection made by said potential detecting means on each retrieval memory word block.

17. The semiconductor integrated circuit of claim 12, further comprising means for driving the plurality of control word lines corresponding to each of said retrieval memory word blocks in a predetermined order.

18. The semiconductor integrated circuit of claim 12, wherein the enable means is a selective transistor.

19. The semiconductor integrated circuit of claim 12, wherein the connection means comprises a first storage unit providing a first circuit path between the match line and the first data line and a second storage unit providing a second circuit path between the match line and the second data line.

20. The semiconductor integrated circuit of claim 19, wherein said first and second storage units each comprises a coupler.

21. The semiconductor integrated circuit of claim 20, wherein each said storage unit is composed of a nonvolatile memory element.

22. The semiconductor integrated circuit of claim 21, wherein said nonvolatile memory element is a MONOS-type nonvolatile memory element.

23. The semiconductor integrated circuit of claim 20, further comprising a common connection line connected to one of the couplers of the first and second storage units of the memory in the plurality of retrieval memory word blocks, the enabling means and couplers of the enable means, and one unidirectional element provided between said common connection line and each of said plurality match lines.

24. The semiconductor integrated circuit of claim 23, further comprising fixing means for fixing an electric potential of said common connection line.

25. The semiconductor integrated circuit of claim 23, wherein each said unidirectional element has a threshold voltage higher than that of any peripheral element.

26. The semiconductor integrated circuit of claim 20, further comprising a common connection line connected to one of the couplers of the first and second storage units of the memory in the plurality of retrieval memory word blocks, said enable means and couplers of the enable means;

a control element provided between said common connection line and said match line; and

a connection means for connecting a gate electrode of said control element to said match line.

27. The semiconductor integrated circuit of claim 26, further comprising fixing means for fixing the electric potential of said match line.

28. The semiconductor integrated circuit of claim 26, wherein said control element has a threshold voltage higher than that of any peripheral element.

29. A semiconductor integrated circuit, comprising:

a match line;

a first data line;

a second data line;

a memory cell, comprising;

connection means for selectively providing a circuit path between the match line and one of the first and second data lines, and

enable means for controllably enabling the circuit path;

a control word line controlling the connection means; and

a control line controlling the enable means;

wherein the control word line and control line control the connection means and enable means to connect the match line to one of the first and second data lines during a data retrieval operation.

30. The semiconductor integrated circuit of claim 29, further comprising potential detecting means for detecting an electric potential of said match line.

31. The semiconductor integrated circuit of claim 29, wherein said match line further has fixing means for fixing an electric potential of said match line.

32. The semiconductor integrated circuit of claim 29, wherein the connection means comprises a first storage unit providing a first circuit path between the match line and the first data line and a second storage unit providing a second circuit path between the match line and the second data line.

33. The semiconductor integrated circuit of claim 32, further comprising a unidirectional element provided between said match line, and one of the first and second storage units and said enable means.

34. The semiconductor integrated circuit of claim 32, wherein each said storage unit comprises a nonvolatile memory element.

35. The semiconductor integrated circuit of claim 34, wherein each of said first and second storage units comprises a nonvolatile memory element, and a connection line of both said nonvolatile memory elements is connected to the enable means.

36. The semiconductor integrated circuit of claim 34, wherein each said nonvolatile memory element is at least one of an EPROM, an EEPROM and an UVEPROM.

37. The semiconductor integrated circuit of claim 34, wherein one of said first and second storage units is a depletion-mode transistor, another of said first and second storage units is an enhancement-mode transistor, and the enable means is connected to each of the depletion-mode and enhancement-mode transistors in series.

38. The semiconductor integrated circuit of claim 34, further comprising potential float means for allowing a potential of the control line to float and connection means for connecting the control line to said match line, said connection means and said potential float means being activated during a data retrieval operation, a potential of said match line becoming positively correlated to the potential of said control line.

39. The semiconductor integrated circuit of claim 29, wherein the enable means is at least one selective transistor provided between at least one of the connection means and the match line and the connection means and the first and second data lines.

40. The semiconductor integrated circuit of claim 39, wherein said at least one selective transistor has a threshold voltage higher than that of any peripheral circuit.

41. The semiconductor integrated circuit of claims 39, wherein said at least one selective transistor is a unidirectional element.

42. The semiconductor integrated circuit of claim 41, wherein said unidirectional element has a threshold voltage higher than that of any peripheral element.

43. A semiconductor integrated circuit, comprising:

a plurality of retrieval memory cells, the plurality of cells arranged in a rectangular matrix array, the array having a plurality of rows of cells and a plurality of columns of cells;

a plurality of control word lines, each control word line associated with a corresponding row of cells;

a plurality of match lines, each match line associated with a corresponding plurality of rows of cells;

a plurality of sets of first and second data lines, each set associated with a corresponding column of cells; and

a plurality of potential detecting means, each potential detecting means connected to a corresponding match line;

wherein each memory cell comprises;

connection means for selectively providing a circuit path between the corresponding match line and one of the first and second data lines of the corresponding set of first and second data lines,

enable means for controllably enabling the circuit path, and

a control line controlling the enable means, wherein the corresponding control word line controls the connection means; and

wherein the corresponding control word line and control line control the connection means of each cell of the corresponding row to establish the circuit paths between the sets of first and second data lines and the corresponding match line during a data retrieval operation.

44. The semiconductor integrated circuit of claim 43, further comprising fixing means for fixing an electric potential of said match line.

45. The semiconductor integrated circuit of claim 43, further comprising potential float means for allowing a potential of the control line to float and connection means for connecting said control line to said match line.

46. The semiconductor integrated circuit of claim 43, further comprising potential float means for allowing a potential of the control word line to float and connection means for connecting the control word line to said match line, said connection means and said potential float means being activated during the data retrieval operation, a potential of said match line becoming positively correlated to the potential of said control word line.

47. The semiconductor integrated circuit of claim 43, further comprising holding means for holding the result of a detection made by said potential detecting means for each retrieval memory word block.

48. The semiconductor integrated circuit of claim 43, further comprising means for driving the plurality of control word lines corresponding to each of said retrieval memory word blocks in a predetermined order.

49. The semiconductor integrated circuit of claim 43, wherein the connection means comprises a first storage unit providing a first circuit path between the match line and the first data line and a second storage unit providing a second circuit path between the match line and the second data line.

50. The semiconductor integrated circuit of claim 49, further comprising at least one selective transistor provided between said match line and said first and second storage units, and a control line for controlling said selective transistor, said control word line and said control line controlling the connection between each of said first and second data lines of the corresponding set of data lines and said corresponding match line connection states of said first and second storage units.

51. The semiconductor integrated circuit of claim 49, wherein one of said first and second storage units in the memory cell is a depletion-mode transistor and another of said first and second storage units is an enhancement-mode transistor.

52. The semiconductor integrated circuit of claim 49, wherein said selective transistor has a threshold voltage higher than that of any peripheral element.

53. The semiconductor integrated circuit of claim 49, wherein each said storage unit comprises a nonvolatile memory element.

54. The semiconductor integrated circuit of claim 53, wherein said nonvolatile memory element comprises at least one of an EPROM, an EEPROM and a UVEPROM.

55. The semiconductor integrated circuit of claim 49, further comprising a common connection line connected to the first and second storage units of each memory block of the plurality of retrieval memory word blocks, wherein said enable means is provided between one end of said common connection line and said match line.

56. The semiconductor integrated circuit of claim 55, further comprising fixing means for fixing an electric potential of said common connection line.

57. The semiconductor integrated circuit of claim 43, wherein the enable means is at least one selective transistor provided between at least one of the connection means and the match line and the connection means and the first and second data lines.

58. The semiconductor integrated circuit of claim 57, wherein said selective transistor is a unidirectional element.

59. The semiconductor integrated circuit of claim 58, wherein said unidirectional element has a threshold voltage higher than that of any peripheral element.

60. A semiconductor integrated circuit, comprising:

a first transistor chain comprising a plurality of serially connected transistors;

a second transistor chain comprising a plurality of serially connected transistors;

a first data line connected to a first end of the first transistor chain;

a second data line connected to a first end of the second transistor chain;

a match line;

potential detecting means for detecting an electrical potential of the match line; and

a selective transistor connecting the match line to second ends of each of the first and second transistor chains.

61. The semiconductor integrated circuit of claim 60, wherein one of enhancement-mode and depletion-mode transistors form said first and second transistor chains, depending on storage data of the first and second data lines, respectively and wherein each transistor chain includes one of an enhancement-mode and a depletion-mode transistor forms at least one of the transistors of said transistor chains as a chain control transistor, irrespective of said storage data.

62. A semiconductor integrated circuit of claim 60, wherein said selective transistor is a unidirectional element.

63. The semiconductor integrated circuit of claim 62, further comprising fixing means for fixing electric potentials of said second ends of said first and second transistor chains.

64. The semiconductor integrated circuit of claim 62, wherein said unidirectional element has a threshold voltage higher than that of any peripheral element.

65. The semiconductor integrated circuit of claim 60, further comprising connection means for connecting said match line to one control line connecting to the gate electrodes of said two selective transistor connected to said first and second selective transistor chains.

66. The semiconductor integrated circuit of claim 65, wherein said selective transistor connected to the second ends of said first and second transistor chains has a threshold voltage higher than that of any peripheral circuit.

67. The semiconductor integrated circuit of claim 65, further comprising mixing means for fixing an electric potential of said match line.

68. The semiconductor integrated circuit of claim 60, further comprising potential float means for allowing a potential of the control line to float and connection means for connecting the control line to said match line, said connection means and said potential float, means being activated during the data retrieval operation, and a potential of said match line is positively correlated to the potential of said control line.

69. The semiconductor integrated circuit of claim 68, further comprising a plurality of word lines for driving respective gates from the outermost transistors among the transistors constituting said first and second transistor chains on one side toward the other side, said plurality of word lines being commonly used for said first and second transistor chains, and holding means for selectively holding results of retrieval from said potential detection means, said holding means corresponding to one of the plurality of word lines other than those used to control said chain control transistor.

70. The semiconductor integrated circuit of claim 69, further comprising means for driving the plurality control lines of each said retrieval memory word block in a predetermined order.

71. The semiconductor integrated circuit of claim 68, wherein said first and second transistor chains each comprises one of enhancement-mode and depletion-mode transistors, depending on the storage data.

72. A semiconductor integrated circuit of claim 61, wherein nonvolatile transistors form parts of said first and second transistor chains.

73. The semiconductor integrated circuit of claim 60, wherein nonvolatile transistors form portions of said first and second transistor chains and wherein one of an enhancement-mode and a depletion-mode transistor forms at least one of the transistors of each said transistor chains as a chain control transistor.

74. The semiconductor integrated circuit of claim 60, further comprising a plurality of word lines driving respective gates from the outermost transistors among the transistors constituting said first and second transistor chains on one side toward the other side, each of said plurality of word lines being commonly connected to said first and second transistor chains, and holding means for selectively holding results of retrieval from said potential detection means, said holding means corresponding to ones ofthe plurality of control lines not used to control said chain control transistor.

75. The semiconductor integrated circuit of claim 74, further comprising means for driving the respective control word lines of said retrieval memory word blocks in order predetermined.

76. A semiconductor integrated circuit comprising:

a transistor;

a first signal line connected to one of a source electrode of the transistor and a drain electrode of the transistor;

a second signal line connected to the other of the source and drain electrodes;

a control word line connected to a gate of the transistor;

connection means for controllably electrically connecting the first signal line to the control word line; and

potential float means for allowing an electrical potential of the control word line to float;

wherein the transistor operates as a unidirectional element between the first signal line and the second signal line when the connection means and potential float means are activated.

77. A semiconductor integrated circuit comprising:

a memory cell;

a match line;

a control word line;

a first data line;

a second data line;

potential float means for allowing a potential of the control word line to float;

connection means for electrically connecting the control word line to the match line; and

control means for operating the potential float means and the connection means during a data retrieval operation so that the potential of the control word line positively correlates to a potential of the match line;

wherein the memory cell comprises a first storage means for providing a first circuit path between the match line and the first data line;

second storage means for providing a second circuit path between the match line and the second data line; and

enable means for controllably enabling one of the first and second circuit paths; and

wherein the potential float means and the first connection means are enabled during a data retrieval operation to allow the potential of the control word line to positively correlate to a potential of the match line.