Semiconductor integrated circuit device and digital processor employing the same

• US 5,388,073 A
• Filed: 04/15/1991
• Issued: 02/07/1995
• Est. Priority Date: 04/16/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Uchida, Akihisa, Usami, Masami, Iwabuchi, Masato, Sakai, Yoshino
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): DINH, SON T
• Application Number:
  US07/685,196
• Time in Patent Office: 1,394 Days
• Field of Search: 365/230.05, 365/230.08, 365/230.09, 365/189.04, 365/205, 365/230.03, 365/207, 307/530, 307/355, 307/356
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory device for use in a digital data processor together with a central processing unit (CPU) receives address signals which are validated for a time period n times as long as the machine cycle of the CPU, and it stores therein input data items which are validated for a cycle equal to the machine cycle of the CPU or delivers therefrom output data items which are validated for a cycle equal to the machine cycle of the CPU.

Claims

1. A semiconductor integrated circuit device comprising:

a plurality of memory blocks each including;

a plurality of memory cells,

a plurality of word lines and a plurality of data lines which are coupled to said memory cells in such a manner that one memory cell is coupled to one word line and one data line, and

decoder means coupled to said plurality of word lines and said plurality of data lines for bringing one of said plurality of word lines and at least one of said plurality of data lines into selected states on the basis of address signals;

wherein the number of said plurality of memory blocks is n, and a cycle time t_c required for one of a read operation and a write operation of said each of said memory blocks is set at;

space="preserve" listing-type="equation">t.sub.c ≦

n×

t.sub.mc

where t_mc denotes a machine cycle of a digital processor, and

wherein said plurality of memory blocks are started sequentially every machine cycle of said digital processor.

7. A semiconductor integrated circuit device according to claim 1, wherein said plurality of memory blocks are formed on one semiconductor substrate.

8. A semiconductor integrated circuit device according to claim 1, wherein said memory cells include flip-flops, respectively.

9. A semiconductor integrated circuit device according to claim 8, wherein each of said flip-flops is comprised of bipolar transistors.

10. A semiconductor integrated circuit device according to claim 1, further comprising:

sense means coupled to said plurality of memory blocks and responsive to a selection signal for amplifying a selected one of the read signals of said plurality of memory blacks.

18. A semiconductor integrated circuit device according to claim 8, wherein said plurality of memory blocks include one pair of memory blocks, and a cycle time t_c required for a read operation and a write operation of said pair of memory blocks is set at:

space="preserve" listing-type="equation">t.sub.c ≦

n×

t.sub.mc

where t_mc denotes a machine cycle of said digital processor, and wherein said pair of memory blocks are simultaneously started so as to bring one of them into a read mode and the other into a write mode.

19. A semiconductor integrated circuit device according to claim 18, wherein each of said pair of memory blocks has its operation mode set at the read mode and the write mode alternately.

2. A semiconductor integrated circuit device comprising:

first and second memory banks each including a plurality of memory blocks, wherein each memory block includes;

a plurality of memory cells,

a plurality of word lines and a plurality of pairs of data lines which are coupled to said memory cells in such a manner that one memory cell is coupled to one word line and one pair of data lines, and

decoder means coupled to said plurality of word lines and said plurality of pairs of data lines for bringing one of said plurality of word lines and at least one of said plurality of pairs of data lines into selected states on the basis of address signals applied thereto;

wherein the number of said plurality of memory blocks in each of said first and second memory banks is n,

wherein the respective memory blocks of said first memory bank and the respective memory blocks of said second memory bank are formed as individual pairs so that one of said plurality of memory blocks in said first memory bank is in a read operation, while one of said plurality of memory blocks in said second memory bank which forms one pair with respect to the one of said plurality of memory blocks in said first memory bank is in a write operation,

wherein said plurality of memory blocks of each of said first and second memory banks are started sequentially every machine cycle of a digital processor, and wherein a cycle time t_c required for a read operation or a write operation of said plurality of memory blocks of each of said first and second memory banks is set at;

space="preserve" listing-type="equation">t.sub.c ≦

n×

t.sub.mc

where t_mc denotes a machine cycle of said digital processor.

3. A semiconductor integrated circuit device according to claim 2, wherein each of said first and second memory banks are set at the read operation and the write operation alternately.

4. A semiconductor integrated circuit device according to claim 3, further comprising a plurality of address counters which form address signals for the read operation and the write operation.

5. A semiconductor integrated circuit device according to claim 2, further comprising a sense amplifier which receives and amplifies a selected one of read signals of said plurality of memory blocks in accordance with a predetermined select signal.

6. A semiconductor integrated circuit device according to claim 5, wherein said sense amplifier includes a plurality of differentially connected pairs of bipolar transistors, having collectors selectively coupled in common.

11. A semiconductor integrated circuit device according to claim 2, wherein said plurality of memory blocks are formed on one semiconductor substrate.

12. A semiconductor integrated circuit device according to claim 2, wherein said memory cells include flip-flops, respectively.

13. A semiconductor integrated circuit device according to claim 12, wherein each of said flip-flops is comprised of bipolar transistors.

14. A semiconductor integrated circuit device comprising:

first and second memory blocks which are controlled so that one of said first and second memory blocks is in a read mode, while the other of said first and second memory blocks is in a write mode, each of said first and second memory blocks includes;

a plurality of memory cells;

a plurality of word lines and a plurality of pairs of data lines which are coupled to said memory cells in such a manner that one memory cell is coupled to one word line and one pair of sad plurality of pairs of data lines, and

decoder means coupled to said plurality of word lines and said plurality of pairs of data lines for bringing one of said plurality of word lines and at least one pair of said plurality of pairs of data lines into selected states on the basis of address signals applied thereto; and

sense means responsive to a selection signal and for amplifying selected ones of first read signals of said first memory block and second read signals of said second memory block, wherein said sense means includes;

a first circuit including first differentially connected bipolar transistors for amplifying one of said first read signals and second differentially connected bipolar transistors for amplifying one of said second read signals, and

a second circuit including a third differentially connected bipolar transistors for amplifying another of said first read signals and a fourth differentially connected bipolar transistors for amplifying another of said second read signals,

wherein a collector of one of said first differentially connected bipolar transistors and a collector of one of said second differentially connected bipolar transistors are coupled in common,

wherein a collector of one of said third differentially connected bipolar transistors and a collector of one of said fourth differentially connected bipolar transistors are coupled in common,

wherein bases of the one of said first differentially connected bipolar transistors and the one of said third differentially connected bipolar transistors are coupled to receive a first selecting signal of said selection signal, and

wherein bases of the one of said second differentially connected bipolar transistors and the one of said fourth differentially connected bipolar transistors are coupled to receive a second selecting signal of said selection signal.

15. A semiconductor integrated circuit device according to claim 14, wherein said plurality of memory cells are static type memory cells which include flip-flop circuits, respectively.

16. A semiconductor integrated circuit device according to claim 15, wherein said flip-flop circuits are comprised of bipolar transistors, respectively.

17. A semiconductor integrated circuit device according to claim 15, wherein said flip-flop circuits are comprised of MOSFETs, respectively.