Flash memory mass storage architecture

• US 5,388,083 A
• Filed: 03/26/1993
• Issued: 02/07/1995
• Est. Priority Date: 03/26/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Estakhri, Petro, Nemazie, Siamack, Assar, Mahmud
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US08/038,668
• Time in Patent Office: 683 Days
• Field of Search: 365/218, 365/900, 365/185, 365/230.03, 365/200
• US Class Current: 365/185.33
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, all blocks in the mass storage are used evenly. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit flag.

Claims

1. A non-volatile semiconductor mass storage device comprising:

a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes; and

b. means for ensuring no block is subjected to more than a predetermined larger number of erase cycles than any other block.

2. The device according to claim 1 wherein the means for ensuring comprises a counter for each block for counting each erase cycle to which that block has been subjected.

3. The device according to claim 2 wherein the counter includes a plurality of bits programmed by binary counting.

4. The device according to claim 2 wherein the counter includes a plurality of bits programmed by sequentially programming each bit, one at a time, wherein each programmed bit represents a count of one.

5. The device according to claim 2 further comprising means for setting a maximum count value which applies to all blocks, and further an erase inhibit flag having a set condition and an unset condition for each block for preventing further erases to a block having its erase inhibit flag in the set condition.

6. The device according to claim 5 further comprising:

a. means for determining whether the counter for any erased block is equal to the maximum count value;

b. means for finding a block having a count value less than the maximum count value; and

c. means for moving the block having a count value less than the maximum count value into an erased block having its counter equal to the maximum count value.

7. The device according to claim 6 further comprising means for finding a block having a then least count value and moving that block into the erased block having its counter equal to the maximum count value.

8. The device according to claim 5 wherein the blocks, the counter and the flag are formed of flash memory cells.

9. The device according to claim 5 wherein the blocks, the counter and the flag are formed of E² PROM cells.

10. A non-volatile semiconductor mass storage device comprising:

a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes; and

b. a controller to ensure no block is subjected to more than a predetermined larger number of erase cycles than any other block.

11. The device according to claim 10 wherein the controller comprises a counter for each block for counting each erase cycle to which that block has been subjected.

12. The device according to claim 11 wherein the counter includes a plurality of bits programmed by binary counting.

13. The device according to claim 11 wherein the counter includes a plurality of bits programmed by sequentially programming each bit, one at a time, wherein each programmed bit represents a count of one.

14. The device according to claim 11 further comprising means for setting a maximum count value which applies to all blocks, and further an erase inhibit flag having a set condition and an unset condition for each block for preventing further erases to a block having its erase inhibit flag in the set condition.

15. The device according to claim 12 further comprising:

a. a first circuit to determine whether the counter for any erased block is equal to the maximum count value;

b. a searcher to find a block having a count value less than the maximum count value; and

c. a second circuit to move the block having a count value less than the maximum count value into an erased block having its counter equal to the maximum count value.

16. The device according to claim 15 further comprising means for finding a block having a then least count value and moving that block into the erased block having its counter equal to the maximum count value.

17. The device according to claim 12 wherein the blocks, the counter and the flag are formed of flash memory cells.

18. The device according to claim 12 wherein the blocks, the counter and the flag are formed of E² PROM cells.

19. A non-volatile semiconductor mass storage device comprising:

a. a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes;

b. a plurality of counters, one counter for each block, to count each time its associated block is erased, wherein a programmable maximum value is applied to all the blocks;

c. a plurality of erase inhibit flags, each flag having a set condition and an unset condition, one flag for each block, wherein the flag for a block having a count value equal to the maximum value is set to prevent further erasing of that block;

d. a controller to switch data in a block having a relatively small count value into a block having the maximum value; and

e. an erase element to clear all counters and all flags once all flags are set.

20. The device according to claim 19 further comprising:

a. means for determining whether the counter for any erased block is equal to the maximum count value;

b. means for finding a block having a count value less than the maximum count value; and

c. means for moving the block having a count value less than the maximum count value into an erased block having its counter equal to the maximum count value.

21. The device according to claim 20 further comprising means for finding a block having a then least counter value and moving that block into the erased block having its counter equal to the maximum count value.

22. The device according to claim 21 wherein the blocks, the counter and the flag are formed of flash memory cells.

23. The device according to claim 21 wherein the blocks, the counter and the flag are formed of E² PROM cells.

24. A method of maintaining parity of erase cycles amongst storage blocks in a non-volatile semiconductor mass storage device having a plurality of non-volatile storage blocks, wherein each block is selectively programmable to store data and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes, the method comprising;

a. counting and maintaining a count value for each block representing each time it is erased;

b. setting a predetermined maximum value;

c. preventing an erase cycle from being performed on a block having a count value equal to the maximum value;

d. switching data from a block having a smallest count value into a block having the maximum value; and

e. erasing the count values once all blocks have been erased the maximum value of times.