Receiving circuit for digital data transmitted by wireless communication

• US 5,388,100 A
• Filed: 09/24/1993
• Issued: 02/07/1995
• Est. Priority Date: 02/26/1993
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ohtsuka, Jun
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US08/126,381
• Time in Patent Office: 501 Days
• Field of Search: 370/66, 370/77, 370/95.3, 370/100.1, 370/95.1, 455/133, 455/134, 455/135, 455/136, 455/277.1, 455/277.2, 375/100, 375/108
• US Class Current: 370/334
• CPC Class Codes: H04B 7/0817 with multiple receivers and antenna path selection
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

A receiving circuit, which prevents spikes included in reproduced clock signals, caused by a time slot change in the division multiplex wireless communication or by the switching of diversity antenna, from being transmitted to the following circuits, and thereby eliminates errors in the determination of the received data, has a demodulator coupled to an antenna for demodulating signals received therefrom, a selector coupled to the demodulator for selecting from a plurality of clock signals reproduced from the data of the respective time slots, one of the reproduced clock signals. A time division timing control circuit is coupled to the selector and to a switching circuit, which control circuit is supplied with an internal clock signal from an internal clock generation circuit. The switching circuit is coupled to the output terminal of the selector and selects and outputs either the internal clock signal or the selected reproduced clock signal. The receiving circuit may be provided with a diversity control circuit.

Claims

1. A receiving circuit which outputs plural time slots of time division multiplexed data transmitted by wireless communication and clock signals reproduced from the data while relating the data and the clock signals, the circuit comprising:

a selector which receives reproduced clock signals of the respective time slots and selects one of said received clock signals reproduced from the data of the respective time slots and outputs said one selected reproduced clock signal;

a time division timing control circuit, coupled to said selector, for separating the received data every time slot and switching an output of said selector in synchronism with the separation;

an internal clock generation circuit for generating an internal clock signal; and

a switching circuit which is supplied with the internal clock signal generated by said internal clock generation circuit and the reproduced clock signal selected by and outputted by said selector, and selects and outputs either the selected reproduced clock signal or the internal clock signal,

said switching circuit including a circuit which selects and outputs the internal clock signal while said time division timing control circuit is switching the output of said selector.

2. A receiving circuit which receives data being transmitted by wireless communication with a plurality of antennas, and outputs the data received by an antenna which is selected by diversity control and a clock signal reproduced from the data while relating the data and the clock signal, the receiving circuit comprising:

a selector which receives clock signals reproduced from the data received by said antennas and selects one of said clock signals reproduced from the data received by the antennas and outputs the selected reproduced clock signal;

a diversity control circuit coupled to said selector, for switching an output of said selector in synchronism with the diversity control;

an internal clock generation circuit for generating an internal clock signal; and

a switching circuit which is supplied with said internal clock signal generated by said internal clock generation circuit and the selected reproduced clock signal outputted by said selector, and selects and outputs either the selected reproduced clock signal or the internal clock signal,

said switching circuit including a circuit which selects and outputs the internal clock signal while said diversity control circuit is switching the output of said selector.

3. A receiving circuit which receives plural time slots of time division multiplexed data transmitted by wireless communication and received on a plurality of antennas, and outputs the plural time slots of data received on an antenna which is selected by diversity control and a clock signal reproduced from the respective data while relating the data and the clock signal, the receiving circuit comprising;

a plurality of selectors each receiving clock signals reproduced from the data of the respective time slots selecting one of said clock signals reproduced from the data of the respective time slots and outputting a selected reproduced clock signal;

a time division timing control circuit, coupled to said selectors, for separating the received data every time slot and switches outputs of said selectors in synchronism with the separation;

a further selector which receives clock signals reproduced from the data received on said antennas and selects and outputs one of the received clock signals reproduced from the data received on said antennas;

a diversity control circuit, coupled to said further selector, for switching an output of said further selector in synchronism with the diversity control;

an internal clock generation circuit for generating an internal clock signal; and

a switching circuit which is supplied with the internal clock signal generated by the internal clock generation circuit and the reproduced clock signal which is outputted by said further selector at inputs thereof, and selects and outputs either the internal clock signal or the selected reproduced clock signal,

the switching circuit including a circuit which selects and outputs the internal clock signal while the time division timing control circuit is switching outputs of said plurality of selectors and the diversity control circuit is switching the output of said further selector.