Gerbil wheel memory

• US 5,388,208 A
• Filed: 12/04/1992
• Issued: 02/07/1995
• Est. Priority Date: 12/04/1992
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Knight, Paul E., Graves, Jennifer A., Short, Paul J., Weingartner, Thomas A.
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US07/985,975
• Time in Patent Office: 795 Days
• Field of Search: 365/189.04, 365/230.05, 395/164, 395/165, 395/166, 395/115, 395/116, 395/725, 395/275, 360/35.1
• US Class Current: 345/544
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A display memory system consisting of a controller and a display memory that has a read display memory cycle time that is a non-integer multiple of the write display memory update rate. The display memory being partitioned into two frames of display memory with each frame having a plurality of subframes. The controller consisting of a read display memory decoder, a read display memory next subframe generator a read display memory latch and consisting of a write display memory decoder, a write display memory next subframe generator and write display memory latch.

Claims

1. A display memory apparatus for use with a graphic display system, which avoids the simultaneous reading from and writing to a single memory location, comprising;

a memory means for storing data wherein the memory means is partitioned into two frames of memory, each of the frames for storing data for a single display screen, and wherein the frames are each partitioned into a plurality of subframes;

a memory controller means coupled to the memory means by a first communication bus and a second communication bus, the memory controller means further coupled to the graphic display system by a write communication bus and a read communication bus, the memory controller means for controlling a transfer of data between the graphic display system and the memory means where the graphic display system has a read rate and a write rate which are not integer multiples of one another, the memory controller means controls the transfer of data by directing the transfer of data to assure that the data is not read from a subframe which is currently being written to.

2. The display memory apparatus of claim 1 wherein the memory controller means further comprises:

a write address means for receiving a write address signal on the write communication bus and producing an input address signal on the first communication bus which identifies the frame and the subframe to be written to wherein each frame is alternately written to and each subframe within the frame is written to consecutively; and

a read address means for receiving a read address signal on the read communication bus and producing an output address signal on the second communication bus which identifies the frame and subframe to be read from, wherein the read address means tests the input address signal and a write clock signal received on the write communication bus to determine which subframe is currently being written to by the write address means and which subframes will be written to during a subsequent read cycle and then produces the output address signal to assure that the write address means and the read address means will not be addressing the same subframe within the next read cycle.

3. The display memory apparatus of claim 2 wherein the write address means comprises a write address decoder, and a write state machine wherein the write address decoder receives the input address signal and produces an end of subframe signal on a decoder output if the write address is a last address of a partitioned subframe, the write state machine receives the end of subframe signal from the write decoder on an input and produces a next subframe address on a write state machine output which is connected to the memory means via the first communication bus.

4. The display memory apparatus of claim 3 wherein the read address means comprises a read address decoder, and a read state machine wherein the read address decoder receives the read address signal and produces an end of subframe signal on a read address decoder output if the read address is the last address of a partitioned subframe, and wherein the read state machine receives the end of subframe signal from the read address decoder on a first input and also receives the next subframe address from the write state machine on a second input, the read state machine then produces a next subframe address on a read state machine output which is connected to the memory means via second communication bus.

5. The display memory apparatus of claim 1 wherein the frames of memory are partitioned into four subframes.

6. The display memory system of claim 4 wherein the read state machine will output an address corresponding to the next subframe within the frame unless the subframe currently being read is the last subframe within its frame, wherein if the subframe currently being read is a last subframe within its frame, the read state machine will output an address corresponding to a first address of the subframe currently being read if the read address and the write address will be the same during a subsequent read cycle, and wherein if the subframe currently being read is the last subframe of its frame, and the read address and the write address will not be the same during the subsequent read cycle, the read state machine will output an address corresponding to the first subframe of the frame not presently being read.

7. The memory display device of claim 1 wherein the write communication bus comprises a write pixel clock line, a write address bus, and a write data bus.

8. The memory display device of claim 1 wherein the read communication bus comprises a read pixel clock line, a read address bus, and a read data bus.

9. The memory display device of claim 1 wherein controller means is a microprocessor.

10. A display memory apparatus for use with a graphic display system, which avoids the simultaneous reading from and writing to a single memory location,

a memory means for storing data having a first addressing port, a second addressing port, a first data port, and a second data port, wherein the memory means is partitioned into a plurality of frames of memory and each frame is partitioned into a plurality of subframes;

a memory controller means having a write addressing port for receiving addressing signals from the graphic display system, a write data port for receiving data from the graphic display system, a read addressing port for receiving read addressing signals from the graphic display system, a read data port for transmitting data to the graphic display system, an input address port connected to the first addressing port for transmitting address signals to the memory means, an input data port connected to the first data port for transmitting data to the memory means, an output address port connected to the second addressing port for transmitting address signals to the memory means, and an output data port connected to the second data port for receiving data from the memory means, the memory controller means for receiving write address signals on the write address port and producing an input address signal on the input address port which identifies a specific frame and a specific subframe within the memory means to which the write data signal is to be stored, the memory controller means also for receiving read address signals on the read address port and producing an output address signal on the output address port which identifies a specific frame and a specific subframe within the memory means from which data is to be retrieved, wherein the memory controller means will control the output address signals so as to assure that the input data will be written to and the output data will be read from different subframes.

11. The display memory apparatus of claim 10 wherein the memory controller means further comprises:

a write address means for receiving the write address signal and producing the input address signal which identifies the frame and subframe to be written to wherein each frame is written to consecutively and each subframe within the frame is written to consecutively; and

a read address means for receiving the read address signal and producing the output address signal which identifies the frame and subframe to be read from wherein the read address means tests the input address signal and an input clock signal to determine which subframe is currently being written to by the write address means and which subframes will be written to during the next read cycle and then produces the output address signal such that the write address means and the read address means will not be addressing the same subframe within the next read cycle.

12. The display memory means apparatus of claim 10 wherein the memory is partitioned into two frames.

13. The display memory apparatus of claim 10 wherein the frames of memory are partitioned into four subframes.

14. The display memory apparatus of claim 12 wherein the frames of memory are partitioned into four subframes.

15. The display memory apparatus of claim 11 wherein the write address means comprises a write address decoder, and a write state machine wherein the write address decoder receives a write address on an input from the graphic display system and produces an end of subframe signal on an output if the write address is a last address within a partitioned subframe, the write state machine receives the end of subframe signal from the write decoder on an input and produces a next subframe address on a write state machine output which is connected to the first addressing port of the memory means.

16. The display memory apparatus of claim 15 wherein the read address means comprises a read address decoder, and a read state machine wherein the read address decoder receives a read address on an input from the graphic display system and produces an end of subframe signal on an output if the read address is the last address of a partitioned subframe, and wherein the read state machine receives the end of subframe signal from the read decoder on a first input and also receives the write next subframe signal from the write state machine on a second input, the read state machine then produces a next subframe address on a read state machine output which is connected to the second addressing port of the memory means.

17. The display memory apparatus of claim 16 wherein the memory is partitioned into two frames.

18. The display memory apparatus of claim 17 wherein the frames of memory are partitioned into four subframes.

19. The display memory of claim 18 wherein the write state machine receives the end of subframe signal from the write decoder and:

a. if the specific subframe currently being written to is not the last subframe within the specific frame currently being written to the write state machine will produce a write next subframe signal which corresponds to the next subframe within the current frame of the memory means; and

b. if the specific subframe currently being written to is the last subframe within the specific frame currently being written to the write state machine will produce a write next subframe signal which corresponds to the first subframe within the alternate frame.

20. The display memory of claim 19 wherein the read state machine receives the read end of subframe signal from the read decoder and the write next subframe signal from the write state machine and:

a. if the read address signal read by the read address decoder was not the last address of a partitioned subframe corresponding to the last subframe of a current frame, the read state machine produces the read next subframe address signal corresponding with the next subframe within the current frame in sequential order; and

b. if the read address signal read by the address decoder was the last address of a partitioned subframe corresponding to the last subframe of the current frame, the read state machine checks the write next subframe address signal and the input clock signal and, if the write address means could address a subframe in the alternate frame at the same time the read addressing means could address that subframe, then the read state machine produces a read next subframe signal which corresponds with the first subframe in the current frame; and

c. if the last read next subframe signal was the address of the last subframe of the current frame, the read state machine checks the write next subframe address and the input clock signal and if the write address means could not address a subframe in the alternate frame at the same point in time time the read addressing means could address that same subframe, then the read state machine produces an read next subframe signal which corresponds with the first subframe in the alternate frame.

21. The display memory system of claim 10 wherein the memory controller means further comprises a read pixel clock port for receiving a read pixel clock signal from the graphic display system.

22. The display memory system of claim 10 wherein the memory controller means further comprises a write pixel clock port for receiving a write pixel clock signal from the graphic display system.

23. A display memory system for use with a graphic display system, comprising

a memory means for storing data having an input addressing port, an input data port, output addressing port, and an output data port, wherein the memory means is partitioned into a first frame of memory and a second frame of memory and wherein the first frame of memory is partitioned into a first subframe, a second subframe, a third subframe, and a fourth subframe, and the second frame of memory is partitioned into a fifth subframe, a sixth subframe, a seventh subframe and an eighth subframe;

and

a memory control means having a read addressing port for receiving read addressing signals from the graphic display system, a read data port for transmitting data to the graphic display system, a write addressing port for receiving write addressing signals from the graphic display system, a write data port for receiving data from the graphic display system, the memory control means further having a control means input address port connected to the memory means input address port for transmitting an input address signal to the memory means, a control means input data port connected to the memory means input data port for transmitting data to the memory means, a control means output address port connected to the memory means output address port for transmitting an output address signal to the memory means, and a control means output data port connected to the memory means output data port for receiving data from the memory means, the memory controller means for controlling a transfer of data to and from the memory means such that data can be written to the memory means and read from the memory means simultaneously and the memory controller further for assuring that data is not written to a subframe which data is concurrently being read from.

24. The display memory apparatus of claim 23 wherein the memory controller means further comprises:

a write address means for receiving the write address signal and producing the input address signal which identifies the frame and subframe to be written to wherein each frame is written to consecutively and each subframe within the frame is written to consecutively; and

a read address means for receiving the read address signal and producing the output address signal which identifies the frame and subframe to be read from wherein the read address means tests the input address signal and an input clock signal to determine which subframe is currently being written to by the write address means and which subframes will be written to during a subsequent read cycle and then produces an appropriate output address signal to assure that the write address means and the read address means will not be addressing the same subframe within the next read cycle.

25. The display memory apparatus of claim 24 wherein the write address means comprises a write address decoder, and a write state machine wherein the write address decoder receives a write address on an input from the graphic display system and produces an end of subframe signal on an output if the write address corresponds to a final address within a partitioned subframe, the write state machine receives the end of subframe signal from the write decoder on an input and produces a next subframe address on a write state machine output which is connected to the first addressing port of the memory means.

26. The display memory apparatus of claim 25 wherein the read address means comprises a read address decoder, and a read state machine wherein the read address decoder receives a read address on an input from the graphic display system and produces an end of subframe address on an output if the read address is the last address of a partitioned subframe, and wherein the read state machine receives the end of subframe signal from the read decoder on a first input and also receives the write next subframe signal from the write state machine on a second input, the read state machine then produces a next subframe address on a read state machine output which is connected to the second addressing port of the memory means.

27. A process for controlling the storage and retrieval of data from a memory wherein the memory is partitioned into two frames of memory and each frame is partitioned into a plurality of subframes, comprising the steps of:

a. writing data to the frames of memory wherein each frame is alternately written and wherein each frame is written to by sequentially writing to each subframe at a writing rate;

b. reading data from the frame of memory which is not being written to, wherein the data is read at a reading rate which is not equal to nor an integral multiple of the writing rate and wherein each frame is read by sequentially reading each subframe within that frame;

c. checking to determine if any subframe in the frame of memory which was not last read from will be written to during an upcoming reading cycle at an identical point in time that subframe could be read from;

d. reading from the frame of memory which was not last read from if no subframe within that frame will be written to at the same time that subframe could be read; and

e. reading from the frame of memory last read from if any subframe in the frame last read from will be written to at the same time that frame could be read.