Efficient channel and control unit for host computer
First Claim
1. An I/O system for controlling transfer of data between a memory of a host processor and a plurality of different types of device controllers, said I/O system comprising:
- a plurality of first programmed means, within an other processor, for determining if a plurality of respective device controller types support specific I/O commands;
second programmed means, within said other processor and responsive to an I/O command to perform an I/O operation on a specific device controller, for identifying and invoking execution of a program within the corresponding first programmed means associated with a type of said specific device controller and, if said specific device controller supports the command, invoking execution of a program within said specific device controller;
third programmed means, within said other processor, for receiving I/O operation state information from said specific device controller and signalling the state information to said second programmed means; and
multitasking operating system means for controlling execution of the program within said corresponding first programmed means and a program within said second programmed means on said other processor in a common task, and a program within said third programmed means on said other processor in a different task.
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Abstract
An I/O system including a processor, a multitasking operating system and DMA hardware efficiently controls a transfer of data between a main memory and memories of different types of devices by minimizing context switches between tasks and wait times of the tasks. A plurality of validation routines are used to validate a plurality of commands when the validation routines are called. Each of the commands corresponds to a specific type of I/O operation and a specific one of the device memories to participate in the I/O operation with the main memory. Each of the validation routines is device type specific and command type specific. A general routine responds to each of the commands by identifying and calling the validation routine which corresponds to the type of I/O operation and type of device which are specified in the command. The general routine initiates I/O hardware after the validation routine validates the command. After the I/O hardware completes the I/O operation, it signals a command completion routine which is command specific and device type specific. In response, the command completion routine signals to the general routine a state of the I/O operation. Each of the validation routines executes on the same task as the general routine to minimize context switches, and each of the command completion routines executes on a different task than the general routine to minimize wait time for the command completion routine.
119 Citations
23 Claims
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1. An I/O system for controlling transfer of data between a memory of a host processor and a plurality of different types of device controllers, said I/O system comprising:
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a plurality of first programmed means, within an other processor, for determining if a plurality of respective device controller types support specific I/O commands; second programmed means, within said other processor and responsive to an I/O command to perform an I/O operation on a specific device controller, for identifying and invoking execution of a program within the corresponding first programmed means associated with a type of said specific device controller and, if said specific device controller supports the command, invoking execution of a program within said specific device controller; third programmed means, within said other processor, for receiving I/O operation state information from said specific device controller and signalling the state information to said second programmed means; and multitasking operating system means for controlling execution of the program within said corresponding first programmed means and a program within said second programmed means on said other processor in a common task, and a program within said third programmed means on said other processor in a different task. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for controlling transfer of data between a memory of a host processor and a plurality of different types of device controllers, said method comprising the steps of:
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receiving a command to perform an I/O operation to a specific device controller, and in response, executing a first sequence of program steps on an other processor to identify and invoke execution of a second sequence of program steps corresponding to a type of said specific device controller; executing said second sequence on said other processor to determine if said specific device controller supports the command, and if so, said first sequence invoking execution of a program within said specific device controller; executing a third sequence of program steps on said other processor to receive information from said specific device controller indicating the state of the I/O operation and signal the state information to said first sequence; and using a multitasking operating system, controlling execution of said first sequence and said second sequence on said other processor in a common task, and said third sequence on said other processor in a different task. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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Specification