Data transmission system which prefetches data to be transferred

• US 5,388,229 A
• Filed: 10/14/1993
• Issued: 02/07/1995
• Est. Priority Date: 04/23/1990
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Hyouga, Yukio, Kaneko, Katsuyuki
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/136,095
• Time in Patent Office: 481 Days
• Field of Search: 395/325, 395/250, 395/400, 395/425, 395/550, 395/575, 395/725, 395/200
• US Class Current: 710/316
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

In a data transmission device, before the starting of data transmission, a data conduct device detects an external bus, and an address comparator section compares the value of the address signal line with the output values of the parameter memory section. As the result of the comparison, when it is judged that the data to be transmitted is present on the external bus, the address comparator section transmits a write-execution signal to a bus control unit so that the bus control unit writes the data present on the external bus together with the validity bit thereof into the data memory device. In the period of data transmission, when the data assigned to the address produced by an address generator is present in the data memory device, the data is transmitted to the external destination, and on the other hand, when the data assigned to the address is absent in the data memory device, the bus control unit gains access to the external memory for obtaining the data corresponding to the address, so that the data obtained from the external memory is transmitted to the external destination.

Claims

1. A data transmission system connected to a common bus for connecting in common a memory for storing data and a processor for processing the data stored in the memory, and for transmitting data, produced by the processor, through a data input/output port to an external destination, said data transmission comprising:

a data conduct device, connected to said common bus, for storing parameters which represent a range of data to be transmitted and for monitoring said common bus to determine whether an access on said common bus is within said range and for generating a data fetch signal;

a data memory device for storing the data to be transmitted; and

a bus control means, connected to said common bus, for reading data to be transmitted from said common bus in response to said data fetch signal from said data conduct device and for writing data into said data memory device;

wherein the parameter for data transmission is set prior to the production of the transmission data by said processor, and wherein said data conduct device monitors the common bus in the period when said processor is producing the transmission data, and when the data to be transmitted appears on the bus, said data conduct device transmits a signal to said bus control means so that said bus control means receives the signal from said data conduct device and causes the data appearing on the common bus to be written into said data memory device, and wherein in the period when data transmission is to be carried out, if data to be transmitted is stored in said data memory device, then the data stored in said data memory device is transmitted to the external destination.

2. The data transmission system according to claim 1, wherein in the absence of data to be transmitted being stored in said data memory device when data transmission is to be carried out, said data conduct device produces an address of data stored in the memory, and wherein said bus control means causes the data stored in the memory to be transmitted to the external destination.

3. A data transmission system connected to a common bus for connecting in common a memory for storing data and a processor for processing the data stored in the memory, and for transmitting data, produced by the processor, through a data input/output port to an external destination, said data transmission system comprising:

a data conduct device which includes;

a parameter memory section for storing parameters which represent a range of data to be transmitted;

an address comparator section, connected to said common bus, for monitoring said common bus and for comparing an address said common bus with said range of data to be transmitted to determine whether an access on said common bus is within said range and for generating a data fetch signal; and

an address generator for producing an address of data to be transmitted to said external destination from the data stored in said parameter memory section and for generating a data request signal;

a data memory device which includes;

a data memory section for storing the data to be transmitted to said external destination and a validity bit memory section for storing validity bits related to the data;

a bus control means connected to said common bus and said data memory device, for reading data to be transmitted from said common bus in response to said data fetch signal and said data request signal from said data conduct device and for writing the data into said data memory device;

wherein the parameter for the data transmission is set prior to the production of the transmission data by said processor, and in the period when said processor is producing the transmission data, said data conduct device monitors the address on said common bus, wherein the address on said common bus is compared with the parameter stored in the parameter memory section by said address comparator section, and when the data on said common bus is in the range of data transmission, said address comparator section transmits a signal to said bus control means so that said bus control means receives the signal from said data conduct device and causes the data on said common bus together with the validity bit to be written into said data memory device;

and wherein when carrying out the data transmission, said address generator sequentially generates the address of the transmission data and said data memory device detects the validity bit corresponding to the address to thereby determine the validity of the data, and when the data stored in said data memory section is determined to be valid, then the data stores in said data memory section is transmitted to said external destination, and when the data in said data memory section is determined to be invalid, then said bus control means access said memory at an address generated by said address generator, whereby data stored in said memory is transmitted to said external destination.

4. A data transmission system according to claim 3, wherein said data memory device further comprises an address memory section for storing the address of the data to be transmitted within the memory, and wherein at the same time said bus control means receives the signal from said data conduct device to write the data on said common bus together with the validity bit into said data memory device, the address on said common bus is written in said address memory section, and when transmitting the data stored in said data memory device, the address generated by said address generator is searched in said address memory section to transmit the data in said data stored memory section corresponding to the address.

5. A data transmission system connected to a common bus for connecting in common a memory for storing data and a processor for processing the data stored in the memory, and for transmitting data, produced by the processor, through a data input/output port to an external destination, said data transmission system comprising:

a data conduct device which includes;

a parameter memory section for storing parameters which represent a range of data to be transmitted; and

an address comparator section, connected to said common bus, for monitoring said common bus and for comparing an address on said common bus with said range of data to be transmitted to determine so as to thereby calculate the transmission order of the data to be transmitted to said external destination;

a data memory device which includes;

a data memory section for storing the data to be transmitted to said external destination using the transmission order as the address; and

a validity bit memory section for storing validity bits related to the data;

a bus control means connected to said common bus and said data memory device, for reading data to be transmitted from said common bus in response to said data fetch signal and said data request signal from said data conduct device and for writing the data into said data memory device;

wherein the parameter for the data transmission is set prior to the production of the transmission data by said processor, and in the period when said processor is producing the transmission data, said data conduct device monitors the address on said common bus, wherein the address on said common bus is compared with the parameter stored in the parameter memory section by said address comparator section, and when the data on said common bus is in the range of data transmission, said address comparator section transmits a signal to said bus control means so that said bus control means receives the signal from said data conduct device and causes the data on said common bus together with the validity bit into said data memory device;

and wherein when carrying out the data transmission, said address generator sequentially generates the address of the transmission data and said data memory device detects the validity bit corresponding to the address to thereby determine the validity of the data, and when the data stored in said data memory section is determined to be valid, then the data stored in said data memory section is transmitted to said external destination, and when the data in said data memory section is determined to be invalid, then said bus control means accesses said memory at an address generated by said address generator, whereby data stored in said memory is transmitted to said external destination.

6. The data transmission system according to claim 5, wherein said data conduct device further includes an address generator for generating the address of the data to be transmitted from the data stored in said parameter memory section, and wherein when carrying out the data transmission, said data memory device sequentially detects the validity bit corresponding to the data stored in said data memory section to thereby determine the validity of the data, and when the data stored in said data memory section is determined to be valid, then the data stored in said data memory section is transmitted to said external destination, and when the data stored in said data memory section is determined to be invalid, then said bus control means accesses said memory at an address generated by said address generator, whereby data stored in said memory is transmitted to said external destination.