History buffer control to reduce unnecessary allocations in a memory stream buffer

• US 5,388,247 A
• Filed: 02/16/1994
• Issued: 02/07/1995
• Est. Priority Date: 05/14/1993
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Goodwin, Paul M., Maskas, Barry A., Thaller, Kurt M.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): TALL, MICHAEL
• Application Number:
  US08/197,376
• Time in Patent Office: 356 Days
• Field of Search: 395/425, 395/400, 364/948, 364/957.9, 364/263.1
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers

Abstract

A read buffering system employs a bank of FIFOs to hold sequential read data for a number of data streams being fetched by a computer. The FIFOs are located in the memory controller, so the system bus is not used in memory accesses used to fill the stream buffer. The system stores addresses used for read requests made by a CPU, and if a next sequential address is then detected in a subsequent read request, this is designated to be a stream (i.e., sequential reads). When a stream is thus detected, data is fetched from DRAM memory for addresses following the sequential address, and this prefetched data is stored in one of the FIFOs. The system also prevents the unnecessary prefetching of data by preventing certain CPU requests from being used to detect streams. A FIFO is selected using a least-recently-used algorithm. When the CPU subsequently makes a read request for data in a FIFO, this data can be returned without making a memory access. By taking advantage of page mode, access to the DRAM memory for the prefetch operations can be transparent to the CPU, resulting in substantial performance improvement if sequential accesses are frequent. The data is stored in the DRAMs with ECC check bits, and error detection and correction (EDC) is performed on the read data downstream of the stream buffer, so the stream buffer is protected by EDC.

Claims

1. A method, comprising the steps of:

receiving from a processor a read command and an address together specifying a memory location to be read;

testing whether said read command is accompanied by an additional indication that said processor will be unable to accept data from said memory location for at least a predetermined time after the issuance of said read command by said processor;

storing an address value corresponding to said memory location into a history buffer and marking the stored value as a valid history buffer entry if said read command is not accompanied by said additional indication, and otherwise refraining from said storing and marking;

repeating the foregoing steps until there is at least one address value stored in said history buffer;

receiving another read command and an address together from said processor specifying another memory location to be read;

testing whether the address of said other memory location has a predetermined relationship with any one of the address values stored in valid entries in said history buffer, the existence of said predetermined relationship indicating that said other memory location sequentially follows the memory location corresponding to the stored address value for which said predetermined relationship exists;

if the address of said other memory location has said predetermined relationship with any of the address values stored in valid entries in said history buffer, asserting a stream detect signal, and otherwise refraining from asserting said stream detect signal;

upon the assertion of said stream detect signal, fetching from a memory the data stored at the memory location sequentially following said other memory location and storing the fetched data in a stream buffer; and

fetching the data stored in said stream buffer and returning it to said processor upon the receipt of a subsequent processor read command specifying said sequentially following memory location.

2. A method according to claim 1, wherein said additional indication comprises an exchange command signifying that said processor must write back data to said memory before said processor will be able to accept the data from said memory location, and wherein said predetermined time is the time required for said processor to perform the write back.

3. A method according to claim 1, wherein the address values stored in said history buffer each result from incrementing a corresponding address accompanying the corresponding read command from said processor, and wherein said step of testing for a predetermined relationship comprises the step of comparing the address of said other memory location with the address values stored in the valid entries in said history buffer to determine whether any of them match.