Method and apparatus for placing an integrated circuit chip in a reduced power consumption state

• US 5,388,265 A
• Filed: 04/26/1993
• Issued: 02/07/1995
• Est. Priority Date: 03/06/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Volk, Andrew M.
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): HAFIZ, TARIQ R
• Application Number:
  US08/053,296
• Time in Patent Office: 652 Days
• Field of Search: 395/750, 395/425, 395/775, 395/800, 364/707, 371/16.3, 371/66
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/325 Power saving in peripheral device

Abstract

A method and apparatus for a chip to monitor its own activity and enter and exit a state of reduced power consumption. The present invention includes defining a predetermined state in which the chip could power down cleanly and monitoring the chip to determine when the chip is in that predetermined state. The present invention also includes a method and apparatus for putting the chip in a state of reduced power consumption state when the chip is in the predetermined state. The present invention also includes a method and apparatus for either turning off the clock generation circuitry or leaving it on during the power down state.

Claims

1. A method for an integrated circuit chip in a computer system to control power consumption automatically, wherein said chip includes core logic and no-core logic to provide internal functionality for the chip and the necessary interface to allow the chip to interact within said computer system and the chip is clocked by a clock input, and further wherein said chip being operable in a plurality of states of operation, said method comprising the steps of:

internally monitoring the core of said chip, said step of internally monitoring being performed by said chip;

determining internally when the core of said chip is in an inactive state;

internally placing said chip in a reduced power consumption state in response to said step of determining indicating that the core of said chip is in said inactive state, said step of internally placing being performed by said chip, wherein the step of internally placing the core of said chip in a reduced power consumption state includes the step of disabling the clock input to the core of said chip;

generating an externally accessible status indication to said computer system when the core of said chip is in the reduced power consumption state, such that said chip appears to said computer system as being powered up, wherein the step of generating the externally accessible status indication includes the step of allowing accesses to the non-core logic while the core remains in the reduced power consumption state; and

powering on said chip on an appropriate request for operation after said chip has been put into said reduced power consumption state, wherein the step of powering on the core of said chip includes the step of enabling the clock input to the core, such that said chip exits the reduced consumption state.

2. The method as defined in claim 1 further comprising the steps of internally determining whether said chip has entered one of said plurality of states of operation, and internally placing said chip back into said reduced power consumption state after a predetermined period of time has elapsed if said chip has not entered one of said plurality of states of operation.

3. The method as defined in claim 1 further comprising the step of putting said chip back into said reduced power consumption state after said chip has been powered up once a predetermined period of time has elapsed if said chip is in said inactive state.

4. The method as defined in claim 1 wherein said chip includes an internal oscillator further comprising the step of allowing said oscillator to run during said reduced power consumption state, such that the core of said chip is clocked instantaneously upon exiting said reduced power consumption state.

5. The method as defined in claim 1 wherein said step of powering on said chip also occurs in response to said chip being reset.

6. The method as defined in claim 1 further comprising the step of placing said chip in an automatic power down mode, such that said chip is placed in the reduced power consumption state automatically when said chip is in said inactive state.

7. The method as defined in claim 6 wherein said step of placing said chip in an automatic power down mode includes the step of sending at least one command to said chip.

8. A method of automatically powering down an integrated circuit chip from within the chip, wherein the chip has core and non-core logic and is clocked by a clock input, and further wherein said chip interacts within a computer system and is operable in a plurality of states of operation, said method comprising the steps of:

internally monitoring the core of said chip, said step of internally monitoring being performed by said chip;

internally placing said chip in the reduced power consumption state when said core logic is inactive;

said step of internally placing being performed by said chip, wherein the step of internally placing the core of said chip in a reduced power consumption state includes the step of disabling the clock input to the core of said chip, such that said non-core logic can be accessed by said computer system without bringing said chip out of said reduced power consumption state;

setting a status indicator indicating that said chip is ready to receive inputs while in the reduced power consumption state;

monitoring a set of interface pins to determine if a command or interrupt is being sent to said chip; and

powering on said chip when said core logic of said chip is requested by said computer system, wherein the step of powering on the core of said chip includes the step of reading the status indicator to determine if said chip is ready and the step of enabling the clock input to the core.

9. An integrated circuit chip for use in a computer system comprising:

core logic to perform a specific function;

non-core logic coupled to the core logic, wherein the non-core logic comprises a first logic circuit to store status of the integrated circuit;

a second logic circuit coupled to the core logic to internally monitoring said core logic;

a third logic circuit coupled to the second logic circuit to determine when the core logic of said chip is in an inactive state; and

a fourth logic circuit coupled to the third logic circuit to place the said chip in a reduced power consumption state in response to said means for determining indicating that said chip is in said inactive state, wherein said fourth logic circuit comprises a clock disabling mechanism to disable the clock input to the core logic of said chip, and

wherein said non-core logic is accessed by said computer system without bringing said core logic out of said reduced power consumption state and wherein said non-core logic stores an externally accessible indication when said chip is in the reduced power consumption state that indicates said chip is ready to receive inputs.

10. The integrated circuit chip defined in claim 9 further comprising a fifth logic circuit on said chip upon request for operation after said chip has been put into said reduced power consumption state, such that said chip exits the reduced power consumption state.

11. The integrated circuit defined in claim 9 wherein the non-core logic comprise at least one register, and further wherein said at least one register receives input from a source external to said chip when said chip is in the reduced power consumption state.

12. An integrated circuit chip for performing a designated function in a computer system comprising:

a bus;

a core logic coupled to said bus to perform said designated function;

a non-core logic coupled to said bus to store the status of said chip and to store input data received from the computer system, wherein the non-core logic comprises a plurality of registers and one of the plurality of registers accessible from a source external to said chip contains a status indicator indicative of the readiness of the chip to receive commands from the computer system;

a first logic circuit coupled to said core logic to internally monitor said core logic to determine when said core logic is inactive; and

a second logic circuit coupled to said first logic circuit to place said core logic in a reduced power consumption state in response to said first logic circuit determining that said core logic is inactive,

wherein the non-core logic receives input data and registers of said plurality of registers are accessible during the reduced power consumption state, and further wherein the status indicator indicates that the chip is ready to receive commands during the reduced power consumption state.

13. The chip defined in claim 12 further comprising a third logic circuit coupled to said core logic to power up said core logic to an active state, wherein said chip is powered on in response to a request for operation after said core logic has been placed in the reduced power consumption state, such that said core logic exits the reduced power consumption state.

14. The chip defined in claim 12 further comprising a plurality of pins to interface to the computer system, wherein a portion of the pins remain active while the chip is in the reduced power consumption state, such that system accesses to said chip are monitored while the chip is in the reduced power consumption state.

15. The chip defined in claim 12 further comprising a clock generation mechanism coupled to said core logic to provide clocking signals to said core logic, wherein said clock generation mechanism includes an oscillator, wherein said oscillator remains powered up while said core logic is in the reduced power consumption state.

16. The chip defined in claim 15 further comprising a clock disabling mechanism coupled to said clock generation means to turn off said oscillator when said core logic in said reduced power consumption state.

17. A computer system comprising a bus, a microprocessor coupled to said bus;

a memory means coupled to said bus for storing data and instructions;

an integrated circuit chip coupled to said bus, said chip including;

a bus;

a core logic coupled to said bus to perform said designated function;

a non-core logic coupled to said bus to store the status of said chip and to store input data received from the computer system, wherein the non-core logic comprises a plurality of registers and one of the plurality of registers contains a status indicator indicative of the readiness of the chip to receive commands from the computer system;

a first logic circuit coupled to said core logic to internally monitor said core logic to determine when said core logic is inactive; and

a second logic circuit coupled to said first logic circuit to place said core logic in a reduced power consumption state in response to said first logic circuit determining that said core logic is inactive;

a third logic circuit coupled to said core logic to power up said core logic to an active state, wherein said chip is powered on in response to a request for operation after said core logic has been placed in the reduced power consumption state, such that said core logic exits the reduced power consumption state,

wherein the non-core logic receives input data and registers of said plurality of registers are accessible during the reduced power consumption state, and further wherein the status indicator indicates that the chip is ready to receive commands during the reduced power consumption state, such that the chip enters and exits the reduced power consumption state transparently to software running in the computer system.