Method of making a semiconductor memory circuit device

• US 5,389,558 A
• Filed: 08/10/1993
• Issued: 02/14/1995
• Est. Priority Date: 11/30/1990
• Status: Expired due to Term

• Current Assignee: Semiconductor Patent Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Watanabe, Kozo, Uchiyama, Hiroyuki, Kaneko, Yoshiyuki, Yoneoka, Takashi, Suwanai, Naokatsu, Endo, Kazuya, Miyazawa, Hiroyuki, Asayama, Kyoichiro, Ogishima, Atushi, Nagao, Masaki, Soeda, Hiroki
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/104,014
• Time in Patent Office: 553 Days
• Field of Search: 437/44, 437/47, 437/48, 437/52, 437/60, 437/919
• US Class Current: 438/241
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

Claims

1. A method for fabricating a semiconductor memory circuit device having an array of memory cells arranged in a matrix form, each memory cell containing a first MISFET and an information storing capacitor connected in series with each other, and also having peripheral circuitry constituted by a plurality of second MISFETs, said method comprising:

(a) a step of forming a first gate electrode of each first MISFET and a second gate electrode of each second MISFET in first and second regions, respectively, on a semiconductor substrate;

(b) after forming the first and second gate electrode, a step of introducing first impurities of N conductivity type into said semiconductor substrate in self-alignment with respect to said first and second gate electrodes in said first and second regions, so as to form a source region and a drain region for said first and second MISFETs;

(c) after introducing the first impurities of N conductivity type, a step of forming a third insulating film in both said first and second regions on said semiconductor substrate;

(d) a step of removing a portion of the third insulating film so as to expose one of the source and drain regions of said first MISFET;

(e) a step of forming a first electrode of said information storing capacitor so as to be in contact with said one of the source and drain regions of said first MISFET exposed through said third insulating film;

(f) a step of forming in sequence, a dielectric film and a second electrode of said information storing capacitor on said first electrode;

(g) a step of forming a second insulating film on said third insulating film in the first and second regions of said semiconductor substrate, after performing steps (e) and (f); and

(h) a step of forming a wiring layer on said second insulating film in said first and second regions, wherein said first and second electrodes extend on said third insulating film in said first region and the thickness of said third insulating film is larger than a total thickness of said first and second electrodes of said information storing capacitor.

2. A method for fabricating a semiconductor memory circuit device according to claim 1, wherein, in step (d), a portion of the third insulating film overlying said first gate electrode is removed.

3. A method for fabricating a semiconductor memory circuit device according to claim 2, wherein, in step (e), an edge of said first electrode is patterned on said third insulating film.

4. A method for fabricating a semiconductor memory circuit device according to claim 1, including the additional step, between steps (g) and (h), of forming holes in said second insulating film so as to expose the other of the source and drain regions of said first MISFET.

5. A method for fabricating a semiconductor memory circuit device according to claim 4, wherein, in the step of forming holes, further holes are formed in said second and third insulating films so as to expose said source and drain regions of said second MISFET.

6. A method for fabricating a semiconductor memory circuit device according to claim 5, further including the steps of forming a fourth insulating film over said wiring layer and forming a further wiring layer over said fourth insulating film.

7. A method for fabricating a semiconductor memory circuit device according to claim 1, wherein the step of forming the second insulating film includes substeps of forming a silicon oxide film and of forming a boro-phospho-silicate glass film on said silicon oxide film.

8. A method for fabricating a semiconductor memory circuit device according to claim 7, further comprising the step of performing an annealing of said boro-phospho-silicate glass film.

9. A method for fabricating a semiconductor memory circuit device according to claim 1, wherein a side face of said third insulating film forms a boundary of said portion of said third insulating film, wherein a portion of said first electrode extends on said side face, and wherein said dielectric film and said second electrode extend on the portion of the first electrode extending on said side face.

10. A method for fabricating a semiconductor memory circuit device according to claim 9, wherein a further portion of the first electrode extends onto an upper surface of the third insulating film, and wherein the dielectric film and the second electrode extend on the further portion of the first electrode that extends onto the upper surface of the third insulating film.

11. A method for fabricating a semiconductor memory circuit device according to claim 1, wherein steps (e) and (f) are performed by forming layers of material of the first electrode, of material of the dielectric film and of material of the second electrode, and removing portions of said layers to form said first electrode, said dielectric film and said second electrode.

12. A method for fabricating a semiconductor memory circuit device according to claim 11, wherein said portions of said layers are removed by etching, the third insulating film acting as an etching stopper for said etching.

13. A method for fabricating a semiconductor memory circuit device according to claim 1, wherein the portion of the third insulating film is removed, in the first region, so as to form a remainder of the third insulating film, in the first region, in the shape of a ring, surrounding said one of the source and drain regions of said first MISFET and exposing said one of the source and drain regions of said first MISFET.

14. A method for fabricating a semiconductor memory circuit device according to claim 13, wherein said ring of the remainder of the third insulating film has first and second side surfaces and an upper surface, and the first electrode is formed such that portions thereof cover the first and second side surfaces and the upper surface.

15. A method for fabricating a semiconductor memory circuit device according to claim 14, wherein said dielectric film and said second electrode cover the portions of the first electrode covering the first and second side surfaces and the upper surface.

16. A method of fabricating a semiconductor memory circuit device according to claim 1, wherein, in step (d), said portion of the third insulating film is removed without removing third insulating film on the second region.

17. A method of fabricating a semiconductor memory circuit device according to claim 1, wherein the second insulating film is formed on the third insulating film in the second region, without having removed third insulating film on the second region.

18. A method of fabricating a semiconductor memory circuit device according to claim 1, wherein said wiring layer is formed in step (h) so as to cover said second electrode of said information storing capacitor in said first region and said second gate electrode in said second region.

19. A method of fabricating a semiconductor memory circuit device according to claim 1, further comprising, between steps (b) and (c):

(i) a step of forming a fifth insulating film on said semiconductor substrate, overlying the first and second gate electrodes;

(j) a step of performing a reactive ion etching of said fifth insulating film so as to form side wall insulating films along end portions of the first and second gate electrodes; and

(k) a step of introducing second impurities of N conductivity type into said semiconductor substrate in self-alignment with respect to said second gate electrode and said side wall insulating film.

20. A method of fabricating a semiconductor memory circuit device according to claim 4, wherein, in the step of forming holes, further holes are formed in the third insulating film so as to expose the other of the source and drain regions of said first MISFET, and wherein said step of forming the wiring layer includes forming the wiring layer in the holes in the second and third insulating films exposing the other of the source and drain regions of said first MISFET, such that the wiring layer is in electrical contact with the other of the source and drain regions of said first MISFET.