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Tamperproof arrangement for an integrated circuit device

  • US 5,389,738 A
  • Filed: 05/04/1992
  • Issued: 02/14/1995
  • Est. Priority Date: 05/04/1992
  • Status: Expired due to Term
First Claim
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1. A tamperproof arrangement for an integrated circuit device comprising:

  • an integrated circuit package including a lid for sealing said integrated circuit package;

    an integrated circuit die including an integrated circuit for providing electronic circuitry;

    die attach material for bonding said integrated circuit die to said integrated circuit package;

    means for detecting a physical attack of said integrated circuit;

    means responsive to said means for detecting for clearing critical information from said integrated circuit;

    said means for detecting including;

    at least two metal conductor grids located only underneath said integrated circuit, said conductor grids for detecting damage to said integrated circuit and providing an indication to said means responsive for clearing said critical information; and

    a dielectric layer interposed between electrode fingers of said two metal conductor grids, in response to damage of said dielectric layer, said dielectric layer indicating a change in capacitance, said means responsive operating to clear said critical information in response to said change in capacitance.

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