Semiconductor diode with reduced recovery current

• US 5,389,815 A
• Filed: 04/20/1993
• Issued: 02/14/1995
• Est. Priority Date: 04/28/1992
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/049,411
• Time in Patent Office: 665 Days
• Field of Search: 257/471, 257/475, 257/481, 257/483, 257/493, 257/496, 257/603, 257/605
• US Class Current: 257/605
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N^- body (2). A P^- layer (4a) is disposed in the top portion of the N^- body (2) so as to be spacewise complementary to the anode P layers (3). In the N^- body (2), P regions (5) are selectively formed below the P^- layer (4a). On the N^- body (2), an anode electrode (6) is disposed in contact with both the P^- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N^- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N^- body (2) is prevented, thereby reducing a recovery current.

Claims

1. A semiconductor device comprising:

a first conductivity type first semiconductor layer;

second conductivity type second semiconductor layers of a relatively high concentration, said second semiconductor layers being selectively formed in a top major surface of said first semiconductor layer;

at least one third semiconductor layer of said second conductivity type having a relatively high concentration, said third semiconductor layer being selectively formed in said first semiconductor layer at a region between neighboring ones of said second semiconductor layers; and

a second conductivity type fourth semiconductor layer of relatively low concentration, said fourth semiconductor layer being formed in said top major surface of said first semiconductor layer at a region between neighboring ones of said second semiconductor layers.

2. The semiconductor device of claim 1, further comprising a first conductivity type fifth semiconductor layer of a higher concentration than the concentration of said first semiconductor layer, said fifth semiconductor layer being disposed under a bottom major surface of said first semiconductor layer.

3. The semiconductor device of claim 2, further comprising a first electrode which is disposed in contact with both said second semiconductor layers and said fourth semiconductor layer.

4. The semiconductor device of claim 3, further comprising a second electrode which is disposed under a bottom major surface of said fifth semiconductor layer.

5. The semiconductor device of claim 4, wherein a plurality of said third semiconductor layers are provided.

6. The semiconductor device of claim 1, wherein said second and said third semiconductor layers are connected to each other.

7. The semiconductor device of claim 6, wherein said third semiconductor layer has a column-like configuration.

8. The semiconductor device of claim 6, wherein said second semiconductor layers surround said fourth semiconductor layer in said major top surface of said first semiconductor layer.

9. The semiconductor device of claim 1, wherein said second and said third semiconductor layers are separated from each other.

10. The semiconductor device of claim 9, wherein said third semiconductor layer has a column-like configuration.

11. The semiconductor device of claim 9, wherein said second semiconductor layers surround said fourth semiconductor layer in said major top surface of said first semiconductor layer.