Variable clock dividing circuit
First Claim
1. A variable clock dividing circuit comprising:
- a plurality of dividing means, coupled in succession, for cooperating to divide an input clock signal by a dividing ratio, said input clock signal being based on a basic clock signal, each of said dividing means outputting an output clock signal based on said input clock signal, clock signals being input to each of said dividing means except a first of said plurality of dividing means being based on said output clock signals of all previous dividing means in said succession;
synchronizing means for synchronizing, based on said basic clock signal, phases of said clock signals being input to said plurality of dividing means except said first of said plurality of dividing means; and
switching means for selectively outputting one of said output clock signals output from said plurality of dividing means.
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Accused Products
Abstract
This variable clock dividing circuit is provided with a plurality of dividers coupled in succession. A first of the dividers divides the basic clock by a predetermined dividing ratio and provides an output clock signal to the next divider in succession, while the last divider receives an output clock signal from the next to last divider. The dividing circuit selectively outputs one of the output block signals from the dividers using a switching circuit. A phase synchronization circuit synchronizes the phase of the clock input to the plurality of dividers based on the basic clock. The phase synchronization circuit further comprises a buffer to delay the basic clock before inputting it to the first divider, and a plurality of AND gates. Each of the AND gates corresponds corresponds to the second to last dividers and receives the basic clock and the outputs from all the preceding dividers.
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Citations
11 Claims
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1. A variable clock dividing circuit comprising:
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a plurality of dividing means, coupled in succession, for cooperating to divide an input clock signal by a dividing ratio, said input clock signal being based on a basic clock signal, each of said dividing means outputting an output clock signal based on said input clock signal, clock signals being input to each of said dividing means except a first of said plurality of dividing means being based on said output clock signals of all previous dividing means in said succession; synchronizing means for synchronizing, based on said basic clock signal, phases of said clock signals being input to said plurality of dividing means except said first of said plurality of dividing means; and switching means for selectively outputting one of said output clock signals output from said plurality of dividing means. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A variable clock dividing circuit comprising:
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a plurality of dividing means for dividing a basic clock signal by a predetermined dividing ratio, each of said dividing means outputting an output clock signal, a first of said dividing means dividing said basic clock signal by a first predetermined dividing ratio and an n-th of said dividing means inputting said output clock signal output from an (n-1)th of said dividing means; synchronization means for synchronizing phases of clock signals being input to said plurality of dividing means based on said basic clock signal; and switching means for selectively outputting one of said output clock signals output from said plurality of dividing means. - View Dependent Claims (8, 9, 10, 11)
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Specification