Apparatus and method for displaying wafer test results in real time

• US 5,390,131 A
• Filed: 04/06/1992
• Issued: 02/14/1995
• Est. Priority Date: 04/06/1992
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Bennett, Michael J., Rohrbaugh, John G., Gil, Mercedes E., Baker, Thomas H., Proulx, Robert W.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US07/863,253
• Time in Patent Office: 1,044 Days
• Field of Search: 364/488-491, 364/552, 364/578, 371/22.1, 371/27, 371/22.3-22.6, 371/29.1, 371/17
• US Class Current: 702/118
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G06F 11/321 Display for diagnostics, e.g. diagnostic result display, self-test user interface

Abstract

The invention is a method for displaying wafer test results from an integrated circuit tester in real time. The method comprising the steps of: (a) receiving wafer dimensions and die dimensions from a wafer handler; (b) creating a template representative of a wafer having cells representative of a die from the wafer dimensions and the die dimensions; (c) displaying the template; (d) invoking a tester to test a selected die of a selected wafer; (e) receiving test results from the tester; (f) displaying the test results on a selected cell which corresponds to the selected die; and (g) repeating steps (d)-(f) as required.

Claims

1. A method in an integrated circuit (IC) production test system controlled by a computer for displaying results of tests executed on dies of a wafer in real time, the method comprising the steps of:

(a) displaying, on a display device of the computer, a template having a plurality of cells, each said cell graphically representing a die on the wafer;

(b) inputting, from an IC tester, a test result for a selected die on said wafer;

(c) presenting an indication of said test result in a selected cell of said template; and

(d) repeating steps (b) and (c) for each die on said wafer.

2. The method of claim 1, wherein step (a) comprises the steps of:

(e) inputting configuration data indicative of wafer dimensions and die dimensions; and

(f) creating said template from said wafer dimensions and said die dimensions.

3. The method of claim 1, wherein step (c) comprises the steps of:

(e) determining from said test result, a major bin classification for said selected die; and

(f) presenting, in said selected cell, an indication of said major bin classification.

4. The method of claim 1, wherein step (c) comprises the steps of:

(e) determining, from said test result, a minor bin classification for said selected die; and

(f) presenting, in said selected cell, an indication of said minor bin classification.

5. The method of claim 1, wherein step (c) comprises the step of coloring said corresponding cell a color indicative of said test result.

6. The method of claim 1, further comprising the step of:

(e) determining and displaying, on said display device, data which enable the user to determine whether the results of the IC tests indicate non-random test failures.

7. The method of claim 1, wherein step (c) comprises the steps of:

(e) determining, from said test result, a fingerprint indicative of which of the tests said die failed; and

(f) presenting said fingerprint on said selected cell.

8. The method of claim 1, wherein step (c) comprises the steps of:

(e) analyzing said test results to determine whether said selected die failed a first test;

(f) if so, then presenting, on said corresponding cell, an indication of said first test;

(g) analyzing said test result to determine a total number of tests that were failed by said selected die;

(h) presenting, in said corresponding cell, an indication of said total number of failed tests;

(i) analyzing said test result to determine a total number of tests executed on said selected die; and

(j) presenting, in said corresponding cell, an indication of said total number of executed tests.

9. An apparatus in an integrated circuit (IC) production test system controlled by a computer for displaying results of tests executed on dies of a wafer in real time, comprising:

means for displaying, on a display device of the computer, a template of cells which graphically represents the dies on the wafer;

means for receiving, from an IC tester, a test result for a selected die on said wafer;

means for presenting an indication of said test result in a selected cell of said template; and

means for repeatedly invoking said receiving means and said presenting means until a test result has been received for each of said dies on said wafer.

10. The apparatus of claim 9, further comprising:

means for receiving configuration data indicative of wafer dimensions and die dimensions; and

means for creating said template from said wafer dimensions and said die dimensions.

11. The apparatus of claim 9, wherein said presenting means comprises:

means for determining, from said test result, a major bin classification for said selected die; and

means for presenting in said corresponding cell an indication of said major bin.

12. The apparatus of claim 9, wherein said presenting means comprises:

means for determining, from said test result, a minor bin classification for said selected die; and

means for presenting, in said selected cell, an indication of said minor bin.

13. The apparatus of claim 9, wherein said presenting means comprises means for coloring said corresponding cell a color indicative of said test result.

14. The apparatus of claim 9, further comprising means for generating and displaying, on said display device, data which enable the user to determine whether the results of the IC tests indicate non-random test failures.

15. The apparatus of claim 9, wherein said presenting means comprises:

means for generating, from said test result, a fingerprint indicative of which of the tests were failed by said die; and

means for presenting said fingerprint on said selected cell.

16. The apparatus of claim 9, wherein said presenting means comprises:

means for analyzing said test results to determine whether said selected die failed a first test;

means for presenting, on said selected cell, an indication of said first test, if said first test exists;

means for analyzing said test result to determine a total number of tests that said selected die failed;

means for presenting, in said selected cell, an indication of said total number of failed tests;

means for analyzing said test result to determine a total number of tests executed on said selected die; and

means for presenting, in said corresponding cell, an indication of said total number of executed tests.

17. The apparatus of claim 9, further comprising means for causing said IC tester to execute a test on said selected die.