Artificial neuron and method of using same
First Claim
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1. A neuron circuit comprising:
- first latch means responsive to a plurality of inputs xi for sequentially storing each of said inputs xi and for sequentially providing each of said stored inputs xi as an output thereof, wherein i is a positive integer;
counter/latch means responsive to the output of said first latch means and providing said stored inputs as an output thereof;
second latch means for providing an output;
a multiplier circuit having a first input responsive to the output of said counter/latch means and a second input responsive to the output of said second latch means, and generating a product;
a multiplexer for coupling either said product or a weight value W to an input of said second latch means; and
wherein said counter/latch means includes means, responsive to a plurality of values gi, there being a value gi corresponding to each value xi, for counting gi multiplication cycles of said multiplier circuit; and
wherein said multiplier includes means for multiplying said input xi by said product during each of said multiplication cycles, and for multiplying said product by said weight value during one of said multiplication cycles;
whereby said neuron circuit generates an output of the form W x1g 1 x2g 2. . . xng n.
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Abstract
An artificial neuron, which may be implemented either in hardware or software, has only one significant processing element in the form of a multiplier. Inputs are first fed through gating functions to produce gated inputs. These gated inputs are then multiplied together to produce a product which is multiplied by a weight to produce the neuron output.
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Citations
7 Claims
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1. A neuron circuit comprising:
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first latch means responsive to a plurality of inputs xi for sequentially storing each of said inputs xi and for sequentially providing each of said stored inputs xi as an output thereof, wherein i is a positive integer; counter/latch means responsive to the output of said first latch means and providing said stored inputs as an output thereof; second latch means for providing an output; a multiplier circuit having a first input responsive to the output of said counter/latch means and a second input responsive to the output of said second latch means, and generating a product; a multiplexer for coupling either said product or a weight value W to an input of said second latch means; and wherein said counter/latch means includes means, responsive to a plurality of values gi, there being a value gi corresponding to each value xi, for counting gi multiplication cycles of said multiplier circuit; and
wherein said multiplier includes means for multiplying said input xi by said product during each of said multiplication cycles, and for multiplying said product by said weight value during one of said multiplication cycles;whereby said neuron circuit generates an output of the form W x1g 1 x2g 2. . . xng n. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification