Core organization and sense amplifier having lubricating current, active clamping and buffered sense node for speed enhancement for non-volatile memory

• US 5,390,147 A
• Filed: 03/02/1994
• Issued: 02/14/1995
• Est. Priority Date: 03/02/1994
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lambrache, Emil, Smarandoiu, George
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/204,866
• Time in Patent Office: 349 Days
• Field of Search: 365/185, 365/210, 365/189.09, 365/189.11, 365/189.05, 365/204, 365/230.03
• US Class Current: 365/185.21
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

Sense amplifier performance is improved in a sense amplifier circuit connected to a semiconductor memory. A current mirror circuit is connected to a data node on the side of a pass transistor adjacent to core memory. The other side of the current mirror circuit is connected to modify the current provided from a memory reference cell. This provides a lubricating current to the pass transistor to ensure that it does not shut down in the absence of current flow from a core memory cell. Sense amplifier speed is improved by a higher transconductance level in the pass transistors. Speed is improved by reducing sense node capacitance through buffer circuitry. Core performance is enhanced by interspersed reference columns within the core at distributed locations.

Claims

1. A sense amplifier circuit connected to a semiconductor memory, comprising:

(a) data node means for receiving an electric current from a selected core memory cell indicative of its memory state;

(b) sense node means for receiving an electric current from said data node means reflecting an electric current received by said data node means;

(c) reference node means for receiving a reference current from a selected reference cell indicative of the state of said reference cell;

(d) a reference current mirror circuit including first and second reference transistors, each reference transistor having respective base, drain, and source nodes, each of the source nodes of said reference transistors being connected to a selected supply voltage, the gate nodes of said first and second reference transistors being electrically connected to each other, the drain node of said first reference transistor being connected to said sense node means and the drain node of said second reference transistor being connected to its gate node and being provided with an electric current from said reference node means reflecting electric currents received by said reference node means, said reference current mirror circuit being effective for providing said sense node means with an electric reference current in proportion to electric current provided from said reference node means to said second reference transistor;

(e) pass transistor means for limiting the voltage on said data node means, said pass transistor means having a source and a drain, said drain being connected to said sense node means, and said source being connected to said data node means; and

(f) a lubrication current mirror circuit including first and second lubrication transistors, each of said lubrication transistors having respective gate, drain, and source nodes, each of the source nodes of said lubrication transistors being connected to a common node, the gate nodes of said first and second lubrication transistors being electrically connected to each other, the drain node of said first lubrication transistor being connected to said data node means and being provided with current from said data node means, the drain node of said first lubrication transistor being connected to its gate node and said data node means, said lubrication current mirror circuit being effective for providing said reference node means and said reference current mirror circuit with electric current in proportion to a lubrication current provided from said data node means to said first lubrication transistor, and said lubrication current mirror circuit being effective for providing a predetermined amount of electric current to said pass transistor means, whereby said pass transistor means remains open even in the absence of current flow from a core memory cell.

2. The sense amplifier circuit according to claim 1, wherein said first and second reference transistors and said first and second lubrication transistors are MOS transistors.

3. The sense amplifier circuit according to claim 2, wherein each of said first and second transistors are connected at a common node.

4. The sense amplifier circuit according to claim 2, wherein each of said first and second transistors are connected at their respective gates.

5. The sense amplifier circuit according to claim 2, wherein said first and second transistors have channels of different sizes with respect to each other.

6. The sense amplifier circuit according to claim 1, wherein said sense node means includes an output amplifying inverter.

7. The sense amplifier circuit according to claim 1, wherein said sense node means includes a buffer circuit for reducing the capacitance seen by said sense node means.

8. The sense amplifier circuit according to claim 7, wherein said buffer circuit includes first and second transistor branches separately driven by said sense node means.

9. The sense amplifier circuit according to claim 8, wherein said first and second transistor branches are connected to a current source.

10. The sense amplifier circuit according to claim 8, wherein said first and second transistor branches comprise exclusively nMOS transistors.

11. The sense amplifier circuit according to claim 1, further comprising clamping means for reducing the voltage swing at said sense node means.

12. The sense amplifier circuit according to claim 11, wherein said clamping means includes a current mirror arrangement for providing a pull down current to the sense node after completion of a low to high transition.

13. A method for providing a sense indication of the memory state of a selected semiconductor memory cell to a sense node connected to a first current mirror circuit for supplying electric current from a reference cell to a sense node, the sense node further being connected to a pass transistor for separating it from the selected memory cell, the pass transistor being connected at its other side to the memory cell, the method comprising the steps of:

(a) connecting a second current mirror circuit to the side of the pass transistor which is on the side of the selected memory cell, and

(b) connecting the other side of the second current mirror circuit to modify the current provided to the first current mirror circuit from the reference cell,

thereby providing a lubricating current to the first current mirror means, and effectively providing current to the pass transistor to ensure that it does not shut down in the absence of current flow from a core memory cell.