Low delay or low loss switch for ATM

• US 5,390,176 A
• Filed: 09/23/1993
• Issued: 02/14/1995
• Est. Priority Date: 04/10/1991
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Awater, Geert A., Schoute, Frederik C.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Nguyen, Chau T.
• Application Number:
  US08/126,146
• Time in Patent Office: 509 Days
• Field of Search: 370/60, 370/60.1, 370/94.1, 370/85.1, 370/85.2, 370/85.6, 370/95.1, 370/13, 370/16, 370/17
• US Class Current: 370/395.7
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5647 Cell loss
• CPC Class Codes: H04L 2012/5649 Cell delay or jitter
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 2012/5682 Threshold; Watermark
• CPC Class Codes: H04L 49/108 using shared central buffer

Abstract

An ATM switching arrangement in which two types of cells are distinguished. A first type of cells is marked as low loss cells and a second type of cells is marked as low delay cells. In the switching arrangement a cell buffer (9) is subdivided into a first memory area (LL) for the low loss cells and a second area (LD) for the low delay cells. In the case of the cell buffer (9) being completely filled, low loss cells get read-in priority over low delay cells. In reading out from the cell buffer low delay cells take priority over low loss cells, unless the low delay area is empty. It is also possible to set a threshold value for the content of the low loss area; when the content of the low loss area exceeds the threshold value outputting of the low loss cells can then be started.

Claims

1. An a telecommunication switching arrangement for switching digital data contained in data cells provided with a cell header, said cell header containing a predetermined location for storing a bit whose value is representative of a cell loss priority of the data cell, the arrangement comprising a crosspoint switch for switching cells from a plurality of input lines of the switch to an output line of the switch, the crosspoint switch further comprising a cell buffer memory for storing the cells to be switched through, the improved arrangement comprising:

(a) the cell buffer memory comprising first and second memory areas, the first memory area for storing first data cells whose predetermined location has a first value representative of a low delay characteristic and the second memory area for storing second data cells whose predetermined location has a second value representative of a low loss characteristic,

(b) means coupled to the input lines for determining the value in said predetermined location of the cell header of each incoming data cell to determine its cell loss priority,

(c) means in said crosspoint switch in response to the determining means determining the first value of an incoming first cell for allocating said incoming first cell to the first memory area and in response to the determining means determining the second value of an incoming second cell for allocating said incoming second cell to the second memory area,

(d) means in said crosspoint switch for reading out for switching purposes to the output line first the cells from the first memory area, unless the number of data cells stored in said second memory area exceeds a predetermined threshold value in which case the data cells stored in the second memory area are read out for switching purposes to the output line.

2. The switching arrangement of claim 1, wherein the means of claim element (b) comprises a queuing element for storing the incoming data cells and an evaluation circuit connected to the queuing element and to the allocating means.

3. The switching arrangement of claim 2, wherein the means of claim element (d) comprises a monitoring means connected to the second memory area for monitoring the number of cells stored therein and in response to the number monitored exceeding the predetermined threshold switching the reading out means to the second memory area.

4. In a telecommunication switching arrangement for switching digital data contained in data cells provided with a cell header, said cell header containing a cell loss priority field for storing a value representative of a cell loss priority of the data cell, the arrangement comprising a crosspoint switch for switching incoming data cells from a plurality of input lines of the switch to an output line of the switch, the crosspoint switch further comprising a cell buffer memory for storing the data cells to be switched through, the improved arrangement comprising:

(a) the cell buffer memory comprising first and second memory areas, the first memory area for storing first cells having a high loss priority value and the second memory area for storing second cells having a low loss priority value,

(b) means coupled to the input lines for determining the value in said cell loss priority field of the cell header of each incoming data cell to determine whether its cell loss priority is a high loss or low loss priority value,

(c) means in said crosspoint switch in response to the determining means determining a high loss priority value of an incoming first cell for allocating said incoming first cell to the first memory area and in response to the determining means determining a low loss priority value of an incoming second cell for allocating said incoming second cell to the second memory area,

(d) means in said crosspoint switch for reading out for switching purposes first the high loss priority cells from the first memory area and for switching to reading out the low loss priority cells from the second memory area when the number of cells stored in said second memory area exceeds a predetermined value.

5. The arrangement of claim 4, wherein arrangement includes storage priority for second cells said determining means of element (c), in response to the cell buffer memory being full, storing incoming second cells having a low loss priority value in the first memory area by replacing first cells having a high loss priority value stored therein.