SONET DS-N desynchronizer

• US 5,390,180 A
• Filed: 02/16/1994
• Issued: 02/14/1995
• Est. Priority Date: 10/10/1991
• Status: Expired due to Term

• Current Assignee: Summit Technology Systems LP
• Original Assignee: NEC America Inc (NEC Corporation)
• Inventors: Reilly, Brian F.
• Primary Examiner(s): MARCELO, MELVIN C
• Application Number:
  US08/197,767
• Time in Patent Office: 363 Days
• Field of Search: 370/84, 370/100.1, 370/102, 370/105.1, 370/105.3, 370/108, 375/118, 359/158
• US Class Current: 370/476
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

A SONET/DS-N desynchronizer and method for receiving an incoming stream of SONET (Synchronous Optical NETwork) data, having a controller for controlling numerically controlled oscillator and clock circuit which provide a desynchronized clock for smoothly adapting the rate at which data is retrieved from a data buffer to the rate at which the incoming SONET data is stored in the data buffer. Pointer adjustments are processed separately from the SONET SPE payload frequency tracking. That is, the processing of pointers, which indicates a change in the phase of the SONET SPE payload, includes detecting negative or positive pointer hits by monitoring, for example, the H1, H2 bytes in the transport overhead, and advancing or retarding the phase over a predetermined period of time. On the other hand, the SONET SPE payload frequency tracking includes detecting positive or negative buffer offsets by monitoring the buffer offset signal OFFSET, and increasing or decreasing, respectively, the tuning word to compensate for the detected positive or negative buffer offset.

Claims

1. An apparatus for receiving a stream of SONET data comprised of overhead information including positive and negative pointer adjustments and a SONET SPE payload for desynchronizing the SONET SPE payload to a DS-N type data, comprising:

first counting means for generating a first count in synchronism with a first clock having a first frequency;

second counting means for generating a second count in synchronism with a desynchronized clock having a second frequency;

buffer means, coupled to said first and second counting means, for storing said SONET SPE payload at a location corresponding to said first count in synchronism with said first clock, and for outputting DS-N type data from a location corresponding to said second count in synchronism with said desynchronized clock;

offset means, coupled to said first and second counting means, for determining a difference between said first count and said second count, and for outputting an offset signal representative thereof;

pointer adjustment means, responsive to said overhead information and said positive and negative pointer adjustments, for monitoring said positive and negative pointer adjustments which respectively indicate the reception of said SONET SPE payload after and before a nominal time, and for outputting a count signal representative of the pointer adjustments accumulated over a predetermined period of time;

clock generating means, responsive to a control signal, for generating said desynchronized clock; and

control means, coupled to said offset means and pointer adjustment means, for generating said control signal in response to said offset signal and said count signal so as to adjust said second frequency of said desynchronized clock such that said difference between said first and second count is maintained at a predetermined value.

2. The apparatus as recited in claim 1, wherein said control means comprises a numerically controlled oscillator for generating said control signal.

3. The apparatus as recited in claim 2, wherein said pointer adjustment means comprises means for producing a phase offset indicative of occurrences of negative and positive pointer adjustments, and wherein said numerically controlled oscillator comprises:

a first register for receiving and storing said phase offset generated by said pointer adjustment means;

a second register for receiving and storing a tuning word generated by said offset means;

a phase accumulator, coupled to an output of said second register, for accumulating changes to said tuning word;

combining means, coupled to an output of said first register and said phase accumulator, for outputting said control signal in accordance with variations in said outputs of said first register and said phase accumulator.

4. The apparatus as recited in claim 3, wherein said combining means comprises an adder for adding said output of said first register and said output of said phase accumulator;

and a lookup table, coupled to an output of said adder, for outputting a digitized form of said control signal.

5. The apparatus as recited in claim 4, wherein said control means further comprises a digital-to-analog converter, coupled to an output of said combining means, for converting said control signal from digital form to analog form.

6. The apparatus as recited in claim 5, wherein said control means further comprises a microcontroller.

7. The apparatus as recited in claim 1, wherein said pointer adjustment means comprises first means for receiving byte pointer adjustment signals representing increases and decreases in pointer adjustments, and second means, coupled to an output of said first means, for counting the number of increases and decreases in pointer adjustments over a predetermined period of time, wherein said output of said second means constitutes said count signal.

8. The apparatus as recited in claim 7, wherein said pointer adjustments are represented by H1 and H2 bytes in the transport overhead section of said SONET data.

9. The apparatus as recited in claim 1, wherein said offset means comprises:

counting means for counting at a predetermined rate when a first pulse is generated, wherein an output of said counting means constitutes said offset signal;

register means for latching said first count when said first pulse is generated; and

means for comparing said second count with said first count and outputting a signal when said second count equals said first count to stop said counting means from counting.

10. The apparatus as recited in claim 1, wherein said clock generating means comprises:

an oscillator for generating a signal having a predetermined frequency; and

a mixer for producing said desynchronized clock having said second frequency which is equal to the sum of a variable frequency and said predetermined frequency, wherein said control signal is varied to adjust said variable frequency such that said second frequency of said desynchronized clock is adjusted to maintain the difference between said first count and said second count at a predetermined value.

11. An apparatus for receiving a stream of SONET data comprised of overhead information including positive and negative pointer adjustments and a SONET SPE payload for desynchronizing the SONET SPE payload to a DS-N type data, comprising:

first clock means for generating a first clock having a first frequency;

second clock means for generating a desynchronized clock having a second frequency;

buffer means, coupled to said first and second clock means, for storing said SONET SPE payload in synchronism with said first clock, and for outputting DS-N type data in synchronism with said desynchronized clock;

offset means for determining a degree of fullness of said buffer, and for outputting an offset signal representative thereof;

pointer adjustment means, responsive to said overhead information and said positive and pointer adjustments, for monitoring said positive and negative pointer adjustments, which respectively indicate the reception of said SONET SPE payload after and before a nominal time, and for outputting a count signal representative of the pointer adjustments accumulated over a predetermined period of time; and

control means, coupled to said offset means and pointer adjustment means, for generating a control signal in response to said offset signal and said count signal so as to vary said second frequency of said desynchronized clock such that said buffer maintains a predetermined degree of fullness.

12. The apparatus as recited in claim 11, wherein said pointer adjustment means comprises first means for receiving byte pointer adjustment signals representing increases and decreases in pointer adjustments, and second means, coupled to an output of said first means, for counting the number of increases and decreases in pointer adjustments over a predetermined period of time, wherein said output of said second means constitutes said count signal.

13. The apparatus as recited in claim 12, wherein said pointer adjustments are represented by H1 and H2 bytes in the transport overhead section of said SONET data.

14. The apparatus as recited in claim 11, wherein said control means comprises a numerically controlled oscillator for generating said control signal.

15. The apparatus as recited in claim 14, wherein said pointer adjustment means comprises means for producing a phase offset indicative of occurrences of negative and positive pointer adjustments, and wherein said numerically controlled oscillator comprises:

a first register for receiving and storing said phase offset generated by said pointer adjustment means;

a second register for receiving and storing a tuning word generated by said offset means;

a phase accumulator, coupled to an output of said second register, for accumulating changes to said tuning word;

combining means, coupled to an output of said first register and said phase accumulator, for outputting said control signal in accordance with variations in said outputs of said first register and said phase accumulator.

16. The apparatus as recited in claim 15, wherein said combining means comprises an adder for adding said output of said first register and said output of said phase accumulator;

and a lookup table, coupled to an output of said adder, for outputting a digitized form of said control signal.

17. The apparatus as recited in claim 16, wherein said control means further comprises a digital-to-analog converter, coupled to an output of said combining means, for converting said control signal from digital form to analog form.