Method and apparatus for processing block instructions in a data processor

• US 5,390,304 A
• Filed: 09/28/1990
• Issued: 02/14/1995
• Est. Priority Date: 09/28/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leach, Jerald G., Simar, Laurence R.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US07/590,372
• Time in Patent Office: 1,600 Days
• Field of Search: 395/400, 395/425, 395/375, 395/800
• US Class Current: 712/241
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/34 Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes address translation G06F12/00
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.

Claims

1. A data processing device comprising:

a clock generator for producing pulses establishing instruction cycles;

a storage circuit for storing therein information accessible by assertion of addresses;

an instruction decode and control unit, connected to said storage circuit, having an instruction register operative to hold a program instruction, said instruction decode and control unit operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction;

a program sequencer circuit, connected to said storage circuit, having a program register operative to hold a program count corresponding to a program address, said program sequencer operative to access information in said storage circuit with the contents of the program register to obtain the program instruction corresponding to the program address;

an arithmetic logic unit, connected to said storage circuit, said program sequencer circuit and said instruction decode and control unit, operative to perform an arithmetic operation on data received by said arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by said instruction decode and control unit to generate a block end address; and

a block handler unit, connected to said instruction decode and control unit, having a block start register operative to store the contents of the program register, responsive to the control signals from said instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed.

2. The data processing device of claim 1 wherein said program sequencer circuit is operative to execute instructions in the block until the contents of the program register are equal to the block end address.

3. The data processing device of claim 1 wherein said block handler unit includes a repeat count register operative to hold a count value equal to how many times the block of instructions is to be executed.

4. The data processing device of claim 1 wherein said block handler unit includes a comparator operative to compare the contents of the program register with the block end address to determine the last instruction of the block of instructions is executed.

5. A data processing system comprising:

a clock generator for producing pulses establishing instruction cycles;

a storage circuit accessible by assertion of addresses;

an instruction decode and control unit, connected to said storage circuit, having an instruction register operative to hold a program instruction, said instruction decode and control unit operative to decode a program instruction providing control signals to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code having a block instruction;

a program sequencer circuit, connected to said storage circuit, having a program register operative to hold a program count corresponding to a program address, said program sequencer operative to access said storage circuit with the contents of the program register to obtain the program instruction corresponding to the program address;

an arithmetic logic unit, connected to said storage circuit, said program sequencer circuit and said instruction decode and control unit, operative to perform an arithmetic operation on data received by said arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by said instruction decode and control unit to generate a block end address;

a block handler unit, connected to said instruction decode and control unit, having a block start register operative to store the contents of the program register, responsive to the control signals from said instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register corresponds to a start address for a block of instructions to be executed; and

a circuit card having external terminals operative to exchange data signals between the storage circuit and the external terminals.

6. A method of operating a data processing device comprising the steps of:

generating pulses establishing instruction cycles;

accessing a storage circuit by assertion of addresses;

performing an arithmetic operation on data;

decoding a program instruction providing control signals to control the operations of the data processing device within each instruction cycle;

accessing said storage circuit by the contents of a program register to obtain a program instruction; and

initiating a block sequence responsive to an instruction code having a block instruction wherein said block sequence comprises the steps of;

generating a block end address by combining the contents of the program register and data decoded from the block instruction;

storing the contents of the program register in a repeat start register;

accessing said storage circuit with the program register containing a program address of a first instruction of a block of instructions; and

comparing the program register containing the program address with the block end address to determine the last instruction in the block of instructions.

7. The method of claim 6 further comprising the step of executing instructions in the block until the contents of the program register are equal to the block end address.

8. The method of claim 6 further comprising the step of counting how many times a block of instructions is executed.