Hardware implemental field oriented bit stream formatter for generating user programmed data formats

• US 5,390,353 A
• Filed: 05/23/1991
• Issued: 02/14/1995
• Est. Priority Date: 05/23/1991
• Status: Expired due to Fees

• Current Assignee: Eastman Kodak Company
• Original Assignee: Eastman Kodak Company
• Inventors: Swanson, Robert E.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): GECKIL, MEHMET B
• Application Number:
  US07/704,556
• Time in Patent Office: 1,363 Days
• Field of Search: 395/200, 395/500, 395/650, 395/800, 395/375, 370/99, 370/94.1, 370/93.1
• US Class Current: 712/210
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G11B 20/12 Formatting, e.g. arrangement of data block or words on the record carriers within interface between computers and data recorders G06F3/06

Abstract

A programmable formatter for providing a data format in response to programmable commands comprises a memory for storing at least program instructions which define the data format; an instruction register for receiving and holding a current program instruction read out of the memory from a given address; a field state machine for indicating when the current program instruction has been completed; an instruction decoder for decoding the program instruction and for specifying information required by a decoded instruction; a repetition counter for counting a number of iterations specified by the current instruction; a data register for storing and outputting fixed patterns specified by the current program instruction; and a next state logic circuit for requesting a next program instruction from the memory when the current program instruction has been completed.

Claims

1. A programmable formatter for formatting digital bit stream information from a cooperating microcomputer digital source, said formatter comprising:

an addressable memory having an address port and a data port for storing program instructions which define a data format,

a next state logic circuit for requesting a next program instruction from said addressable memory upon completion of execution of a current program instruction,

an instruction register for receiving and holding said current program instruction read out of said data port of said memory from a given address provided by said next state logic circuit;

a field state machine, coupled to said memory to receive instruction length information from said next state logic circuit, for indicating when said current program instruction has been completed and for requesting said next program instruction from said addressable memory be transferred to said instruction register;

instruction decoder, coupled to said instruction register to receive said current program instruction read out from said data port, for decoding said current program instruction;

a repetition counter, coupled to said instruction decoder, for counting a number of iterations of portions of said digital information as specified by said current program instruction;

a data register, coupled to said instruction decoder, for storing and outputting programmed data packets of said digital information as specified by said current program instruction;

said formatter further wherein each program instruction defines at least one of a field and field set of the data format, wherein a field set is a collection of fields of said digital information occurring in a specified order;

said formatter further wherein each program instruction includes a length portion for setting a length of each field, a content portion for indicating the content of each field, and a control portion for specifying a control for each program instruction; and

wherein the content portion of each program instruction specifies one of a defined internal pattern and a variable external pattern.

2. A programmable formatter according to claim 1, wherein the control portion specifies one of a load instruction and a branch instruction.

3. A programmable formatter according to claim 2, wherein the load instruction identifies at least one of the repetition counter and the data register and a value to be entered.

4. A programmable formatter according to claim 3, wherein the branch instruction specifies a condition for the branch instruction, an address of the branch when the condition is satisfied and an enable signal for indicating completion of the branching instruction.

5. A programmable formatter according to claim 4, wherein internal patterns are stored in said memory at given addresses.

6. A programmable formatter according to claim 5, wherein said instruction decoder has a control output port for requesting one of a variable external pattern and external control signals.

7. A programmable formatter according to claim 6, wherein said next state logic circuit includes a control input port for receiving external control signals.

8. A programmable formatter according to claim 7, wherein said data register comprises a plurality of data registers and wherein a multiplexer is further provided for selecting a given one of the plurality of data registers for output of the fixed pattern stored thereby.