Rapid reprogramming terminal

• US 5,390,356 A
• Filed: 01/11/1994
• Issued: 02/14/1995
• Est. Priority Date: 05/05/1992
• Status: Expired due to Fees

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Houlberg, Christian L.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): DARBE, VALERIE A
• Application Number:
  US08/182,958
• Time in Patent Office: 399 Days
• Field of Search: 395/200, 395/800, 395/725, 364/242.5, 364/260, 364/260.1, 364/260.2, 364/260.3, 364/926, 364/942
• US Class Current: 703/23
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 8/61 Installation

Abstract

A rapid reprogramming terminal for reprogramming all electronic warfare andvionics systems aboard an aircraft including the bus controllers for each avionics or electronic warfare bus on the MS-1553 multiplex data bus in the aircraft and the remote terminals connected to each bus in the aircraft. The rapid reprogramming terminal includes a high speed digital signal processor which executes the functions required to reprogram a remote terminal or bus controller through software stored in an electrically erasable program read only memory. The information required to reprogram a remote terminal or bus controller is stored on an IC memory card which is electrically coupled to the digital signal processor. When the rapid reprogramming terminal establishes communications with either an avionics bus or electronic warfare bus by enabling certain discretes associated with the bus, the digital data required to reprogram, for example, a remote terminal is transferred from the IC memory card through the digital signal processor in a parallel format to a 1553 communications interface controller. The controller converts the digital data to Manchester encoded differential data for transfer via the MS-1553 multiplex data bus to the remote terminal or bus controller being reprogrammed.

Claims

1. An apparatus for reprogramming a plurality of remote terminals and a plurality of bus controllers connected to a first communications bus, said first communications bus being a command/response time division multiplex data bus, said reprogramming apparatus interfacing with a second communications bus, said reprogramming apparatus comprising:

an integrated circuit memory card;

transceiver means for receiving data from said second communications bus and transmitting data to said second communications bus, said transceiver means formatting the data received thereby to a digital format, the data received from said second communications bus being used to reprogram said remote terminals and said bus controllers connected to said first communications bus;

digital signal processor means for providing a plurality of data transfer control signals, a plurality of address signals and a plurality of data bytes, said digital signal processor means having direct access to said integrated circuit memory card such that data to and from said second communications bus is transferred between said integrated circuit memory card and said second communications bus via said transceiver means and said digital signal processor means;

first programmed array logic means for receiving said data transfer control signals from said digital signal processor means and for decoding said data transfer control signals to control the transfer of data between said second communications bus and said integrated circuit memory card, said integrated circuit memory card storing said data therein;

said first programmed array logic means upon decoding said data transfer control signals generating at least one read signal and at least one write signal;

memory means electrically coupled to said digital signal processor means, said memory means containing software for said digital signal processor means, said software controlling the handling and interpretation of data to and from said first and second communications buses by enabling the operation of said digital signal processor means to accommodate the use of said digital signal processor means with the bus standards, data protocols and formats of said first and second communications buses;

second programmed array logic means for receiving at least one of said data transfer control signals and at least some of said address signals from said digital signal processor means, said second programmed array logic means decoding said data transfer control signals and said address signals received thereby to provide a transceiver select signal to enable said transceiver means, a plurality of interface select signals and a bus controller select signal;

programmed interface means for receiving at least two of said address signals and said data bytes from said digital signal processor means, said interface select signals from said second programmed array logic means and said read signal and said write signal from said first programmed array logic means;

said programmed interface means in response to said at least two address signals, said interface select signals, said data bytes, said read signal and said write signal selectively enabling either one of said remote terminals or one of said bus controllers for reprogramming; and

bus controller means for providing an interface between said digital signal processor means and said first communications bus, said bus controller means formatting the reprogramming data being supplied to said remote terminal or said bus controller being reprogrammed in accordance with the bus standards, data protocols and formats of said first communications bus;

said second programmed array logic means providing said bus controller select signal to said bus controller means enabling said bus controller means allowing said bus controller means to control the transfer of reprogramming data from said digital signal processor means via said first communications bus to said remote terminal or said bus controller being reprogrammed;

said digital signal processor controlling the transfer of reprogramming data from said integrated circuit memory card to said bus controller means.

2. The reprogramming apparatus of claim 1 wherein said first communications bus is a Military Standard 1553 multiplex data bus.

3. The reprogramming apparatus of claim 1 wherein said second communications bus is an RS-232 communications bus.

4. The reprogramming apparatus of claim 1 wherein said memory means comprises an electrically erasable programmed read only memory.

5. The reprogramming apparatus of claim 1 wherein said programmed interface means comprises:

first, second and third programmable peripheral interfaces, each of said programmable peripheral interfaces being electrically coupled to said digital signal processor means, said first programmed array logic means and said second programmable array logic means;

each of said programmable peripheral interfaces receiving said at least two address signals and said data bytes from said digital signal processor means, said read signal and said write signal from said first programmed array logic means and one of said interface select signals from said second programmed interface;

each of said programmable peripheral interfaces being enabled by one of said interface select signals;

each of said programmable peripheral interfaces having first, second and third eight bit output ports, said address signals controlling the selection of the output port to be enabled and said read and write signals enabling the selected output port;

said first, second and third programmable peripheral interfaces providing at each enabled output thereof between one and eight discrete logic signals in response to one of said data bytes; and

said discrete logic signals when supplied to said first communications bus selectively enabling one of said remote terminals or one of said bus controllers for reprogramming allowing said selected remote terminal or said selected bus controller to be reprogrammed by said reprogramming apparatus.

6. The reprogramming apparatus of claim 1 wherein said bus controller being reprogrammed is an AN/AYK-14 computer.

7. The reprogramming apparatus of claim 1 wherein said bus controller being reprogrammed comprises an AN/ALR-67 Radar Warning Receiver.

8. The reprogramming apparatus of claim 1 wherein said remote terminal being reprogrammed comprises an AN/ALQ-126B Defensive Electronic Counter Measures Set.

9. An apparatus for reprogramming a plurality of remote terminals and a plurality of bus controllers connected to a first communications bus, said first communications bus being a command/response time division multiplex data bus, said reprogramming apparatus interfacing with a second communications bus, said reprogramming apparatus comprising:

an integrated circuit memory card;

first transceiver means for receiving data from said second communications bus and transmitting data to said second communications bus, said first transceiver means formatting the data received thereby to a digital format, the data received from said second communications bus being used to reprogram said remote terminals and said bus controllers connected to said first communications bus;

digital signal processor means for providing a plurality of data transfer control signals, a plurality of address signals and a plurality of data bytes, said digital signal processor means having direct access to said integrated circuit memory card such that data to and from said second communications bus is transferred between said integrated circuit memory card and said second communications bus via said first transceiver means and said digital signal processor means;

first programmed array logic means for receiving said data transfer control signals from said digital signal processor means and for decoding said data transfer control signals to control the transfer of data between said second communications bus and said integrated circuit memory card, said integrated circuit memory card storing said data therein;

said first programmed array logic means upon decoding said data transfer control signals generating at least one read signal and at least one write signal;

memory means electrically coupled to said digital signal processor means, said memory means containing software for said digital signal processor means, said software controlling the handling and interpretation of data to and from said first and second communications buses by enabling the operation of said digital signal processor means to accommodate the use of said digital signal processor means with the bus standards, data protocols and formats of said first and second communications buses;

second programmed array logic means for receiving at least one of said control signals and at least some of said address signals from said digital signal processor means, said second programmed array logic means decoding said control signals and said address signals received thereby to provide a first transceiver select signal to enable said first transceiver means, a second transceiver select signal, a plurality of interface select signals and a bus controller select signal;

programmed interface means for receiving at least two of said address signals and said data bytes from said digital signal processor means, said interface select signals from said second programmed array logic means and said read signal and said write signal from said first programmed array logic means;

said programmed interface means in response to said at least two address signals, said interface select signals, said data bytes and said read and said write signals selectively enabling either one of said remote terminals or one of said bus controller for reprogramming; and

bus controller means for providing an interface between said digital signal processor means and said first communications bus, said bus controller means formatting the reprogramming data being supplied to said remote terminal or said bus controller being reprogrammed in accordance with the bus standards, data protocols and formats of said first communications bus;

said second programmed array logic means providing said bus controller select signal to said bus controller means enabling said bus controller means allowing said bus controller means to control the transfer of reprogramming data from said digital signal processor means via said first communications bus to said remote terminal or said bus controller being reprogrammed;

said digital signal processor controlling the transfer of reprogramming data from said integrated circuit memory card to said bus controller means; and

second transceiver means electrically coupled to said digital signal processor means and a third communications bus, said second transceiver means being enable by said second interface select signal from said second programmed array logic means allowing said digital signal processor means to communicate with said third communications bus;

said second transceiver means receiving said read signal and write signal from said first programmed array logic means, said read signal and said write signal controlling a direction of a data transfer between said digital signal processor means and said second transceiver means.

10. The reprogramming apparatus of claim 9 wherein said second communications bus is an RS-422 communications bus.

11. The reprogramming apparatus of claim 9 wherein said second communications bus is an IEEE-488 communications bus.