Active device constructed in opening formed in insulation layer and process for making same

• US 5,391,505 A
• Filed: 11/01/1993
• Issued: 02/21/1995
• Est. Priority Date: 11/01/1993
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Kapoor, Ashok K.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Chaudhari, C.
• Application Number:
  US08/147,290
• Time in Patent Office: 477 Days
• Field of Search: 437/40, 437/51, 437/195, 437/984, 148/DIG. 126, 148/DIG. 164
• US Class Current: 438/152
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Claims

1. A process for forming an MOS type active device at least partially in an opening in an insulation layer over a semiconductor substrate which comprises:

a) forming a first source/drain region in a semiconductor substrate;

b) forming an insulation layer over said semiconductor substrate;

c) forming a first opening in said insulation layer extending down to said semiconductor substrate and in at least partial registry with said first source/drain region in said substrate;

d) forming a semiconductor channel portion on the sidewall of said first opening in said insulation layer with a first end in electrical communication with said first source/drain region;

e) forming a second source/drain region on said insulation layer adjacent said channel portion in said first opening and in electrical communication with a second end of said semiconductor channel portion in said first opening;

f) forming a gate oxide over said semiconductor channel portion; and

g) forming a gate electrode over said gate oxide.

2. The process of claim 1 wherein said step of forming said first source/drain region is carried out prior to forming said insulation layer over said substrate.

3. The process of claim 1 wherein said step of forming said first source/drain region is carried out after forming said opening in said insulation layer over said substrate.

4. The process of claim 1 wherein said step of forming said semiconductor channel portion on said sidewall of said opening in said insulation layer further comprises the steps of:

a) depositing a semiconductive material in said opening; and

b) anisotropically etching said semiconductive material in said opening to remove a central portion of said semiconductor material, thereby leaving a peripheral portion of said semiconductor material on said sidewall of said opening to form said channel portion.

5. The process of claim 1 wherein said step of forming said second source/drain region on said insulation layer adjacent said channel portion in said opening and in electrical communication with said second portion of said semiconductor channel portion in said opening further comprises:

a) forming a doped semiconductor layer over said insulation layer; and

b) patterning said doped semiconductor layer to provide said second source/drain region adjacent said opening in said insulation layer.

6. The process of claim 1 wherein said step of forming said second source/drain region on said insulation layer adjacent said channel portion in said opening and in electrical communication with said second portion of said semiconductor channel portion in said opening further comprises:

a) forming a semiconductor layer over said insulation layer;

b) patterning said semiconductor layer; and

c) doping said patterned semiconductor layer to form said second source/drain region adjacent said opening in said insulation layer.

7. The process of claim 5 wherein said steps of forming and patterning said second source/drain region on said insulation layer are carried out prior to said step of forming said opening in said insulation layer.

8. The process of claim 7 including the further step of forming a second insulation layer over said doped semiconductor layer prior to said step of forming said opening in said insulation layer.

9. The process of claim 8 wherein said step of forming said second insulation layer over said doped semiconductor layer is carried out prior to said step of patterning said doped semiconductor layer.

10. The process of claim 1 including the further steps of forming an MOS type active device in said semiconductor substrate having a first source/drain region common to said first source/drain region of said MOS type active device at least partially formed in said opening in said insulation layer.

11. The process of claim 1 including the further step of forming a second MOS type active device at least partially in a second opening formed in said insulation layer, said second MOS type active device having a first source/drain region common to said first source/drain region of said first MOS type active device at least partially formed in said first opening in said insulation layer.

12. The process of claim 1 including the further steps of:

a) forming an MOS type active device in said semiconductor substrate having a first source/drain region common to said first source/drain region of said first MOS device at least partially formed in said opening; and

b) forming a second MOS type active device at least partially in a second opening formed in said insulation layer, said second MOS device having a first source/drain region common to said common first source/drain region of said MOS type active device formed in said substrate and said first MOS device formed in said first opening in said insulation layer.

13. The process of claim 1 including the further steps of:

a) forming an MOS type active device in said semiconductor substrate having a first source/drain region common to said first source/drain region of said MOS device constructed at least partially in said first opening; and

b) forming a resistor in a second opening in said insulation layer having a first end in electrical communication with said common first source/drain region of said MOS device formed in said substrate and said MOS device constructed at least partially in said first opening in said insulation layer.

14. The process of claim 1 including the further steps of:

a) forming an MOS type active device in said semiconductor substrate having a first source/drain region common to said first source/drain region of said MOS device constructed at least partially in said first opening in said insulation layer; and

b) forming a resistor in an opening in a second insulation layer, said resistor having a first end in electrical communication with said common first source/drain region of said MOS device formed in said substrate and said MOS device constructed at least partially in said first opening in said insulation layer.

15. A process for forming two or more MOS type active devices, at least one of which is at least partially constructed in an opening in an insulation layer over a semiconductor substrate which comprises forming a first MOS type active device by the steps of:

a) forming a first source/drain region in a semiconductor substrate which will provide a common source/drain region of both of said MOS devices;

b) forming an insulation layer over said semiconductor substrate;

c) forming a first opening in said insulation layer extending down to said semiconductor substrate and in at least partial registry with said first source/drain region in said substrate;

d) forming a semiconductor channel portion on the sidewall of said first opening in said insulation layer and having a first portion in electrical communication with said first source/drain region;

e) forming a second source/drain region on said insulation layer adjacent said channel portion in said first opening and in electrical communication with a second portion of said semiconductor channel portion in said opening;

f) forming a gate oxide over said semiconductor channel portion; and

g) forming a gate electrode over said gate oxide; and

forming a second MOS type active device by the steps of;

a) forming a channel region in said substrate adjacent said common first source/drain region in said substrate;

b) forming a gate oxide formed over said channel region in said substrate;

c) forming a gate electrode formed over said gate oxide formed over said channel region in said substrate; and

d) forming a second source/drain region in said substrate adjacent an opposite end of said channel region formed in said substrate.

16. A process for forming two or more MOS type active devices, both of which are at least partially constructed in an insulation layer over a semiconductor substrate which comprises forming a first MOS type active device by the steps of:

a) forming a first source/drain region in a semiconductor substrate;

b) forming an insulation layer over said semiconductor substrate;

c) forming a first opening in said insulation layer extending down to said semiconductor substrate and in at least partial registry with said first source/drain region in said substrate;

d) forming a semiconductor channel portion on the sidewall of said opening in said insulation layer and having a first portion in electrical communication with said first source/drain region;

e) forming a second source/drain region on said insulation layer adjacent said channel portion in said opening and in electrical communication with a second portion of said semiconductor channel portion in said opening;

f) forming a gate oxide over said semiconductor channel portion; and

g) forming a gate electrode over said gate oxide; and

forming a second MOS type active device by the steps of;

a) forming a second opening in said insulation layer in communication with said first source/drain region of said first MOS device;

b) forming a semiconductor material on the sidewall of said second opening in said insulation layer, comprising a channel portion of said second MOS device in electrical communication, at one end thereof, with said first source/drain region in said substrate;

c) forming a second source/drain region, in communication with an opposite end of said channel portion of said second MOS device, on said insulation layer adjacent said second opening therein and in electrical communication with an opposite end of said channel portion formed in said second opening in said insulation layer;

d) forming a gate oxide layer over said channel portion of said second MOS device; and

e) forming a gate electrode over said gate oxide.

17. A process for forming first, second, and third MOS type active devices, at least two of which are at least partially constructed in an insulation layer over a semiconductor substrate which comprises forming a first MOS type active device by the steps of:

a) forming a first source/drain region in a semiconductor substrate which will be common to said first, second, and third MOS devices;

b) forming an insulation layer over said semiconductor substrate;

c) forming a first opening in said insulation layer extending down to said semiconductor substrate and in at least partial registry with said first source/drain region in said substrate;

d) forming a semiconductor channel portion on the sidewall of said first opening in said insulation layer and having a first portion in electrical communication with said first source/drain region;

e) forming a second source/drain region on said insulation layer adjacent said channel portion in said first opening and in electrical communication with a second portion of said semiconductor channel portion in said first opening;

f) forming a gate oxide over said semiconductor channel portion; and

g) forming a gate electrode over said gate oxide;

forming a second MOS type active device by the steps of;

a) forming a channel region in said substrate adjacent said common first source/drain region in said substrate;

b) forming a gate oxide formed over said channel region in said substrate;

c) forming a gate electrode formed over said gate oxide formed over said channel region in said substrate; and

d) forming a second source/drain region in said substrate adjacent an opposite end of said channel region in said substrate; and

forming a third MOS type active device by the steps of;

a) forming a second opening in said insulation layer in communication with said common first source/drain region of said first and second MOS type active devices;

b) forming a semiconductor material on the sidewall of said second opening in said insulation layer, comprising a channel portion of said third MOS device in electrical communication, at one end thereof, with said common first source/drain region in said substrate;

c) forming a second source/drain region, in communication with an opposite end of said channel portion of said third MOS type active device, on said insulation layer adjacent said second opening therein and in electrical communication with an opposite end of said channel portion formed in said second opening in said insulation layer;

d) forming a gate oxide layer over said channel portion of said third MOS device; and

e) forming a gate electrode over said gate oxide.