Process for forming copper interconnect structure

• US 5,391,517 A
• Filed: 09/13/1993
• Issued: 02/21/1995
• Est. Priority Date: 09/13/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Gelatos, Avgerinos V., Fiordalice, Robert W.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): EVERHART, CARIDAD
• Application Number:
  US08/120,097
• Time in Patent Office: 526 Days
• Field of Search: 437/190, 437/189, 437/192, 437/198
• US Class Current: 438/643
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A copper metallization structure and process for the formation of electrical interconnections fabricated with pure copper metal is provided. The metallization structure includes an interface layer (22) intermediate to a dielectric layer (12), and a copper interconnect (30). The interface layer (22) functions to adhere the copper interconnect (30) to a device substrate (10) and to prevent the diffusion of copper into underlying dielectric layers. The interconnect layer (22) is fabricated by depositing a first titanium layer (16) followed by the sequential deposition of a titanium nitride layer (18), and a second titanium layer (20). A copper layer (24) is deposited to overlie the second titanium layer (20) and an annealing step is carried out to form a copper-titanium intermetallic layer (26). The titanium nitride layer (18) functions as a diffusion barrier preventing the diffusion of copper into the underlying dielectric layer (12), and the copper titanium intermetallic layer (26) provides an adhesive material, which adheres the copper layer (24) to the device substrate ( 10). Following the formation of the intermetallic layer (26), the device surface is planarized to form a planar surface (28), and to form an inlaid copper interconnect (30).

Claims

1. A process for fabricating a semiconductor device comprising the steps of:

providing a device substrate having a dielectric layer thereon;

forming an interface layer overlying the dielectric layer, wherein the interface layer includes at least a diffusion barrier layer and a refractory metal adhesion layer overlying the barrier layer;

forming a copper layer overlying the interface layer; and

annealing the substrate to form an intermetallic layer between the copper layer and the interface layer, wherein the copper layer is in intimate contact with intermetallic layer.

4. The process of claim 1, wherein the step of annealing the substrate comprises rapid thermal annealing at less than atmospheric pressure.

5. The process of claim 4, wherein the rapid thermal annealing is performed at a system pressure of 10 to 20 millitorr.

6. The process of claim 1, wherein the step of forming a copper layer comprises metal-organic-chemical-vapor-deposition of copper using a copper β

-diketonate precursor.

2. A process for fabricating a semiconductor device comprising the steps of:

providing a device substrate having a dielectric layer thereon;

forming an interface layer overlying the dielectric layer, wherein the interface layer includes at least a diffusion barrier layer and an adhesion layer,

wherein the adhesion layer comprises first and second titanium layers, and the diffusion barrier layer comprises a titanium nitride layer intermediate to the first and second titanium layers; and

forming a copper layer overlying the interface layer; and

annealing the substrate to form an intermetallic layer between the copper layer and the interface layer, wherein the copper layer is in intimate contact with intermetallic layer.

3. The process of claim 2, wherein the second titanium layer overlies the titanium nitride layer and is deposited to a thickness of 10 to 20 nanometers.

7. A process for fabricating a semiconductor device comprising the steps of:

providing a device substrate having a dielectric layer thereon;

forming a cavity in the dielectric layer;

forming an interface layer overlying the dielectric layer and the cavity, wherein the interface layer includes at least a titanium nitride layer and a titanium layer;

forming a copper layer overlying and in intimate contact with the interface layer and filling the cavity;

annealing the substrate to form a copper-titanium intermetallic layer between the copper layer and the interface layer; and

removing portions of the copper layer, the intermetallic layer, and the interface layer overlying the dielectric layer to form a smooth surface.

8. The process of claim 7, wherein the step of removing comprises chemical-mechanical-polishing using a non-selective slurry.

9. The process of claim 7, wherein the step of forming a cavity comprises reactive ion etching of the dielectric layer.

10. The process of claim 7, wherein the step of forming a copper layer comprises metal-organic-chemical-vapor deposition of copper using a copper β

-diketonate precursor.

11. The process of claim 7, wherein the step of annealing the substrate comprises rapid thermal annealing at less than atmospheric pressure.

12. The process of claim 7, wherein the interface layer comprises first and second titanium layers, and a titanium nitride layer intermediate to the first and second titanium layers.

13. A process for fabricating a semiconductor device comprising the steps of:

providing a device substrate having a dielectric layer overlying a metal interconnect layer;

forming an opening in the dielectric layer to expose a portion of the metal interconnect layer;

forming an interface layer overlying the dielectric layer and the exposed metal interconnect layer, wherein the interface layer includes at least a titanium nitride layer and a titanium layer;

forming a copper layer overlying and in intimate contact with the interface layer and filling the opening;

annealing the substrate to form a copper-titanium intermetallic layer between the copper layer and the interface layer; and

removing portions of the copper layer, the intermetallic layer, and the interface layer overlying the dielectric layer to form a smooth surface.

14. The process of claim 13, wherein the interface layer comprises first and second titanium layers, and a titanium nitride layer intermediate to the first and second titanium layers.

15. The process of claim 13, wherein the step of removing comprises chemical-mechanical-polishing using a non-selective slurry.