Lateral insulated gate field effect semiconductor

• US 5,391,908 A
• Filed: 10/22/1993
• Issued: 02/21/1995
• Est. Priority Date: 03/22/1991
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Walker, Philip, Paxman, David H.
• Primary Examiner(s): Loke, Steven Ho Yin
• Application Number:
  US08/141,467
• Time in Patent Office: 487 Days
• Field of Search: 257/336, 257/339, 257/343, 257/409, 257/408
• US Class Current: 257/409
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor body (1) has a first region (2) of one conductivity type adjacent one major surface (3). Second and third regions (5 and 6) of the opposite conductivity type are provided within the first region (2) adjacent the one major surface (3) and an insulated gate structure (80) overlies a conduction channel region (9) between the second and third regions (5 and 6) for providing a gateable connection along the length (L) of the conduction channel region (9) between the second and third regions (5 and 6). The insulated gate structure (80) has a gate insulating region (81) and a gate conductive region (82) extending on the gate insulating region (81) and up onto a relatively thick insulating region (4) adjoining the gate insulating region (81). The gate insulating region (81) overlaps with the periphery (6a) of the portion (62) of the third region (6) adjacent the insulated gate structure (80) so that, in a direction (D) transverse to the length (L) of the conduction channel region (9), the gate conductive region (82) extends from the gate insulating region (81) up onto the relatively thick insulating region (4) over the first region (2). The corner (10b) at which the gate insulating region (81) adjoins the relatively thick insulating region (4) thus lies over the first region (2) and not over the third region (6), thereby reducing the electric field stress at the corner (10b).

Claims

1. A lateral insulated gate field effect semiconductor device, comprising a semiconductor body having a first region of a first conductivity type adjacent one major surface, second and third regions of a second conductivity type opposite to said first conductivity type provided within the first region adjacent the one major surface and an insulated gate structure overlying a conduction channel region between the second and third regions for providing a gateable connection along a length of the conduction channel region between the second and third regions, the insulated gate structure having a gate insulating region and a gate conductive region extending on the gate insulating region and up onto a relatively thick insulating region adjoining the gate insulating region, characterized in that the gate insulating region overlaps with a periphery of a first portion of the third region adjacent the insulated gate structure and, in a channel width direction of the conduction channel region, a portion of the gate conductive region at a corner of a window in said relatively thick insulating region extends from the gate insulating region up onto the relatively thick insulating region only over the first region, and in that the insulated gate structure is provided within said window in the relatively thick insulating region and a width of said first portion of the third region is of smaller width than a width of the window in the channel width direction of the conduction channel region so that in said channel width direction the third region does not extend beyond the periphery of the window.

2. A device according to claim 1, further characterized in that the window is substantially rectangular, having first and second parallel edges lying along a direction of the length of the conduction channel region, and the first portion of the third region does not extend beyond the first and second edges in said channel width direction.

3. A device according to claim 1, further characterized in that the first portion of the third region is a first relatively lowly doped portion which extends from a second relatively lowly doped portion of the third region towards the second region.

4. A device according to claim 3, further characterized in that a relatively highly doped portion of the third region lies within the relatively lowly doped portion of the third region.

5. A device according to claim 3, further characterized in that a relatively highly doped portion of the third region is provided under a further window in the relatively thick insulating region.

6. A device according to claim 3, further characterized in that the gate conductive region extends over the first relatively lowly doped portion of the third region.

7. A device according to claim 1, further characterized in that the second and third regions form the source and drain regions, respectively, of an insulated gate field effect transistor.

8. A lateral insulated gate field effect semiconductor device as in claim 1, wherein the gate conductive region extends laterally beyond the entirety of the periphery of the third region.