Reach-through isolation silicon-on-insulator device

• US 5,391,911 A
• Filed: 04/22/1994
• Issued: 02/21/1995
• Est. Priority Date: 03/29/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yapsir, Andrie S., Beyer, Klaus D.
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Kelley, Nathan K.
• Application Number:
  US08/231,100
• Time in Patent Office: 305 Days
• Field of Search: 257/347, 257/353, 257/354, 257/506, 257/522, 257/524
• US Class Current: 257/522
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.

Claims

1. A semiconductor chip having isolated islands comprising:

a substrate;

a first heavily doped epitaxial layer on said substrate;

a second lightly doped epitaxial layer on said first layer;

a pair of spaced deep trenches defining one dimension of said islands, said deep trenches extending from the top surface of said second layer, through said first layer and into said substrate, each said deep trench having interior walls comprising sidewalls and a bottom surface, the bottom surface being located within said substrate;

an insulating layer on the interior walls of said deep trenches, said insulating layer extending along the sidewalls of said deep trenches from the top surface of said second layer, through said first layer and into said substrate, said insulating layer further covering the bottom surfaces of said deep trenches; and

a pair of spaced shallow trenches extending fully between said deep trenches and defining a second dimension of said islands, said shallow trenches extending from the top surface of said second layer to said substrate;

said first layer covering said substrate except at the locations of said islands, said deep trenches and said shallow trenches;

said islands being spaced from said substrate by an amount equal to the thickness of said first layer.

2. The chip defined in claim 1 wherein (i) said shallow trenches and (ii) the spaces between said islands and said substrate are filled with dielectric material including air.

3. The chip defined in claim 2 wherein said dielectric material further includes at least one dielectric of the group consisting of silicon dioxide, polysilicon and polymer.

4. The chip defined in claim 1 wherein said first and second layers are N⁺ and N^- doped silicon, respectively.

5. The chip defined in claim 1 wherein a space interior to said insulating layer on the interior walls of each said deep trench is filled with one of the group consisting of polysilicon and borosilicate glass, and further wherein the resulting filled space is capped with silicon dioxide.

6. A semiconductor chip having isolated islands comprising:

a substrate;

a first heavily doped epitaxial layer on said substrate, said first heavily doped epitaxial layer comprising N⁺ doped silicon;

a second lightly doped epitaxial layer on said first layer, said second lightly doped epitaxial layer comprising N^- doped silicon;

a pair of spaced deep trenches defining one dimension of said islands, said deep trenches extending from the top surface of said second layer, through said first layer and into said substrate, each said deep trench having interior walls comprising sidewalls and a bottom surface, the bottom surface being located within said substrate;

an insulating layer on the interior walls of said deep trenches, said insulating layer extending along the sidewalls of said deep trenches from the top surface of said second layer, through said first layer and into said substrate, said insulating layer further covering the bottom surfaces of said deep trenches, wherein a space interior to said insulating layer on the interior walls of each said deep trench is filled with one of the group consisting of polysilicon and borosilicate glass, and further wherein the resulting filled space is capped with silicon dioxide; and

a pair of spaced shallow trenches extending fully between said deep trenches and defining a second dimension of said islands, said shallow trenches extending from the top surface of said second layer to said substrate;

said first layer covering said substrate except at the locations of said islands, said pair of deep trenches and said pair of shallow trenches;

said islands being spaced from said substrate by an amount equal to the thickness of said first layer.

7. The chip defined in claim 6 wherein (i) said shallow trenches and (ii) the spaces between said islands and said substrate are filled with dielectric material including air.

8. The chip defined in claim 7 wherein said dielectric material further includes at least one dielectric of the group consisting of silicon dioxide, polysilicon and polymer.