Semiconductor device having peripheral metal wiring

• US 5,391,920 A
• Filed: 07/08/1992
• Issued: 02/21/1995
• Est. Priority Date: 07/09/1991
• Status: Expired due to Term

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Tsuji, Nobuaki
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): BROWN, PETER T
• Application Number:
  US07/910,624
• Time in Patent Office: 958 Days
• Field of Search: 257/207, 257/203, 257/211, 257/758, 257/775, 257/734, 257/773, 257/920
• US Class Current: 257/758
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/92 Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

At a peripheral area of a semiconductor chip where active elements are not formed, a layer underlying a power supply wiring or ground wiring is provided with an uneven surface. The uneven or corrugated surface at the interface between the wiring and the underlying layer makes the wiring unsusceptible to slide. The uneven surface can be realized by interposing foreign matters between insulating layers, by selectively reducing the thickness of an insulating layer, or by forming openings in an insulating layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an active region;

an insulating layer provided on said semiconductor substrate;

a first metal layer provided on said insulating layer and having first predetermined width, wherein said first metal layer has a plurality of first projections toward said active region;

a second metal layer provided above said first metal layer and having second predetermined width, wherein said second metal layer has a plurality of second projections toward said first metal layer, wherein said first and second projections are disposed in said first and second metal layers over a span longer than said first width and said second width and wherein said first and second projections are provided alternately; and

an insulating interlayer provided between said first and second metal layers.

2. A semiconductor device according to claim 1 wherein the first and second projections are aligned in a plurality of rows.

3. A semiconductor device according to claim 1 wherein the second width of the second metal layer is larger than the first width of the first metal layer.

4. A semiconductor device comprising:

a semiconductor substrate on which a device is provided;

a plurality of power supply lines provided above a peripheral region of the semiconductor substrate for supplying power to the device, each of the plurality of power supplying lines comprising;

a first metal layer having a first predetermined width and having a plurality of first projections toward the region; and

a second metal layer provided above the first metal layer and having a second predetermined width and having a plurality of second projections toward the first metal layer, wherein the first and second projections are alternately provided over a span longer than the first predetermined width and second predetermined width.

5. A semiconductor device according to claim 4 further comprising:

an insulating layer provided on the semiconductor substrate; and

an insulating interlayer provided between the first and second metal layers.

6. A semiconductor device according to claim 4 wherein the first and second projections are alternately provided in a plurality of rows.

7. A semiconductor device according to claim 4 wherein the second width of the second metal layer is larger than the first width of the first metal layer.