Assertive latching flip-flop

• US 5,391,935 A
• Filed: 07/22/1993
• Issued: 02/21/1995
• Est. Priority Date: 07/22/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chung, Paul W., Gersbach, John E.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/096,102
• Time in Patent Office: 579 Days
• Field of Search: 307/289, 307/270, 307/571, 307/272.2, 307/272.3, 307/570, 307/542, 307/291, 328/206
• US Class Current: 327/198
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/2885 the input circuit having a differential configuration

Abstract

An assertive latching flip-flop circuit is provided which prevents the occurrence of metastable outputs. The circuit comprises a single flip-flop which is comprised of standard switching transistors which are switched by a clocking mechanism having no additionally introduced delay. The circuit includes an imbalancing element which is coupled to a latching portion of the circuit. The latching portion of the circuit comprises a pair of cross-coupled transistors, in current mode embodiments of the invention, or a pair of cross-coupled inverters, in voltage mode embodiments of the invention. The imbalancing element introduces an electrical disturbance on the input line to one of the latching transistors or inverters. The imbalancing element is a capacitor in voltage mode embodiments of the invention and an additional transistor in current mode embodiments.

Claims

1. A flip-flop circuit, comprising:

a switching portion having at least three inputs and a first data output;

a clock input and a complementary, synchronous inverted clock input coupled to, respectively, first and second at least three inputs of said switching portion;

at least one data input coupled to a third of said at least three inputs of said switching portion, said complementary clock inputs and said at least one data input being switched asynchronously with respect to each other;

a latching portion coupled to said first data output of said switching portion for providing at least a second data output, said latching portion comprising a pair of transistors arranged in cross-coupled configuration such that an input of a first transistor is coupled to said first data output of said switching portion and to an output of a second transistor by a first conductive path and an input of said second transistor is coupled to an output of said first transistor by a second conductive path; and

a third transistor coupled to one of said first or second conductive paths wherein a base of said third transistor is coupled to said clock input by a first resistor and coupled to said inverted clock input by a second resistor, and an emitter of said third transistor is coupled to an external current source, for preventing said first and second data outputs from assuming a metastable state.

2. The circuit of claim 1, wherein said switching portion of said circuit comprises a plurality of interconnected switching transistors.

3. The circuit of claim 1, wherein said first and second data outputs comprise a pair of data outputs of opposite polarity and said at least one data input comprises a pair of data inputs of opposite polarity.

4. A flip-flop circuit, comprising:

a switching portion having a plurality of inputs and a first data output;

at least one clock input coupled to one of said plurality of inputs of said switching portion;

at least one data input coupled to another one of said plurality of inputs of said switching portion, said at least one clock input and said at least one data input being switched asynchronously with respect to each other;

a latching portion coupled to said first data output of said switching portion for providing at least a second data output, said latching portion comprising a pair of inverters arranged in cross-coupled configuration such that an input of a first inverter is directly coupled to said first data output of said switching portion and to an output of a second inverter by a first conductive path and an input of said second inverter is directly coupled to an output of said first inverter by a second conductive path; and

a capacitor coupled at one end to one of said first or second conductive paths, and at another end to the clock input of said plurality of inputs of said switching portion, for preventing said data output from assuming a metastable state.

5. The circuit of claim 4, wherein said at least one clock input comprises a noninverted clock input and an inverted clock input.

6. The circuit of claim 5, wherein said inverted clock input and said noninverted clock input are complements of each other and are not separated by a time delay.

7. The circuit of claim 5, wherein said capacitor is coupled at one end to either said inverted or noninverted clock input and at the other end to the output of said first inverter.

8. The circuit of claim 5, wherein said switching portion comprises first and second field effect transistors.

9. A flip-flop circuit, comprising:

a switching portion having first through fourth inputs and first and second data outputs of opposite polarity;

a noninverted clock input and an inverted clock input coupled, respectively, to said first and second inputs of said switching portion;

a pair of data inputs of opposite polarity coupled, respectively, to said third and fourth inputs of said switching portion, said clock inputs and said data inputs being switched asynchronously with respect to each other;

a latching portion coupled to said first and second data outputs of said switching portion, said latching portion comprising first and second transistors arranged in cross-coupled configuration such that an input of said first transistor is coupled to said first data output of said switching portion and to an output of said second transistor by a first conductive path, and an input of said second transistor is coupled to said second data output of said switching portion and to an output of said first transistor by a second conductive path; and

an imbalancing transistor coupled to one of said first or second conductive paths for preventing said data output from assuming a metastable state, wherein a base of said imbalancing transistor is coupled to said noninverted clock input by a first resistor and coupled to said inverted clock input by a second resistor, and an emitter of said imbalancing transistor element is coupled to an external current source.

10. A flip-flop circuit, comprising:

a switching portion comprising first and second field effect transistors each providing a gate input, a source input, and a drain output, said gate inputs of said first and second field effect transistors coupled, respectively, to an inverted clock input and a noninverted clock input, both of said source inputs of said first and second field effect transistors coupled to a data input, said clock inputs and said data input being switched asynchronously with respect to each other, said drains of said first and second field effect transistors tied together to provide a first data output;

a latching portion coupled to said first data output of said switching portion for providing at least a second data output, said latching portion comprising first and second inverters arranged in cross-coupled configuration such that an input said first inverter is coupled to said first data output of said switching portion and to an output said second inverter by a first conductive path and an input of said second inverter is coupled to an output of said first inverter by a second conductive path; and

a capacitor coupled at one end to one of said first or second conductive paths, and at another end to said gate input of said first field effect transistor for preventing said data output from assuming a metastable state.