×

Bit compression circuit used for a delta sigma type digital-to-analog converter

  • US 5,392,040 A
  • Filed: 02/23/1993
  • Issued: 02/21/1995
  • Est. Priority Date: 02/24/1992
  • Status: Expired due to Fees
First Claim
Patent Images

1. A bit compression circuit for decreasing the number of bits of digital data used for a delta sigma type D/A converter which converts input digital data into analog signals, said bit compression circuit comprising:

  • a quantization circuit which samples input digital data represented by a predetermined number of bits fed during a digital data input period on a sampling period shorter than the digital data input period and converts the sampled data into quantized digital data having a fewer number of bits than the input digital data;

    a first adder for calculating quantization noise data generated during quantization from the difference between the input data and output data of said quantization circuit;

    a first delay circuit which delays the quantization noise data output by said first adder for said sampling period for outputting delayed quantization noise data;

    a second adder which adds the quantization noise data delayed for said sampling period which is output by said delay circuit and digital data fed into said quantization circuit;

    an integrator into which said delayed quantization noise data is fed for integrating the same; and

    selective addition means for selectively adding output of said integrator to data fed into said quantization circuit.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×