Sigma-delta analog-to-digital converter with filtration having controlled pole-zero locations, and apparatus therefor
First Claim
1. An analog-to-digital converter for converting band-limited analog signals into time- and amplitude-quantized digital signals, said converter comprising;
- analog first summing means (202) including a noninverting input port (254) adapted for receiving said band-limited analog signals, and for receiving an analog replica of an intermediate digital signals, for subtracting said analog replica from said analog signals to form a difference signals;
N-bit analog-to-digital conversion means (210) coupled for receiving resonated signals derived from said difference signals, for generating samples of intermediate digital signals, said analog-to-digital conversion means being subject to quantizing noise;
N-bit digital-to-analog conversion means (218) coupled to said analog-to-digital conversion means (210), for converting said intermediate digital signals into said analog replica of said intermediate digital signals, and for coupling said analog replica to said first summing means (202);
decimating filter means (108) coupled to said analog-to-digital conversion means (210) for digitally low-pass filtering said intermediate digital signals for suppressing said quantizing noise, and for generating digital output signals representing said band-limited analog signals; and
resonator means (758) coupled to said analog-to-digital conversion means (210) and also coupled to said first summing means (202) for receiving said difference signals therefrom, and for filtering said analog difference signals, whereby a feedback loop is formed which tends to suppress said quantizing noise, said resonator means (758) including;
(a) second summing means (762) coupled to said first summing means for receiving said difference signals therefrom and for adding to said difference signals at least first and second weighted delayed feedback signals, for generating undelayed first summed signals;
(b) first weighting means (7661) coupled to an output (763) of said second summing means (762) for weighting said undelayed first summed signals by a first weight to generate weighted undelayed intermediate signals;
(c) third summing means (764) coupled to said first weighting means (7661) for summing said weighted undelayed intermediate signals with at least first weighted delayed feedforward signals to produce said resonated signals;
(d) a nonintegrating first cascade including the cascade of (d1) nonintegrating delay means (7681) and (d2) second weighting means (7701), said first cascade being coupled between said output (763) of said second summing means (762) for delaying and weighting said undelayed first summed signals, said delaying being by a first delay period, and said weighting being with a second weight, for producing said first weighted delayed feedback signals;
(e) a nonintegrating second cascade including the cascade of (e1) nonintegrating delay means (7681) and (e2) third weighting means (7662), said second cascade being coupled between said output (763) of said second summing means (762) and an input of said third summing means (764) for delaying and weighting said undelayed first summed signals, said delaying being by a second delay period, and said weighting being with a third weight (AR2), for producing said first weighted delayed feedforward signals;
(f) a nonintegrating third cascade including the cascade of (f1) nonintegrating delay means (7681, 7682) and (f2) fourth weighting means (7702), said third cascade being coupled between said output (763) of said second summing means (762) and an input of said second summing means (762) for delaying and weighting said undelayed first summed signals, said delaying being by a third delay period, and said weighting being with a fourth weight, for producing said second weighted delayed feedback signals.
2 Assignments
0 Petitions
Accused Products
Abstract
A sigma-delta (ΣΔ) analog-to-digital converter (ADC) accepts band-limited analog signals, and subtracts an analog replica of an output pulse- or amplitude-density modulated (ADM) signal therefrom to produce an error signal. The error signal is processed by an analog filter or resonator with a nondelayed forward path and a tapped nonaccumulating delay line, and summed feedback and feedforward weights coupled to the taps, to thereby produce a resonated signal. An ADC processes the resonated signal, and produces the ADM signal. The ADC undesirably produces quantization noise. A digital-to-analog converter (DAC) noiselessly converts the PDM signal into the analog replica, to aid in forming the error signal. In a particular embodiment of the invention, the resonator includes a recursive analog transversal filter with delays and linear weighting elements for linearity and high operating speed. The ADC may be in a high-speed system such as a radar.
-
Citations
14 Claims
-
1. An analog-to-digital converter for converting band-limited analog signals into time- and amplitude-quantized digital signals, said converter comprising;
-
analog first summing means (202) including a noninverting input port (254) adapted for receiving said band-limited analog signals, and for receiving an analog replica of an intermediate digital signals, for subtracting said analog replica from said analog signals to form a difference signals; N-bit analog-to-digital conversion means (210) coupled for receiving resonated signals derived from said difference signals, for generating samples of intermediate digital signals, said analog-to-digital conversion means being subject to quantizing noise; N-bit digital-to-analog conversion means (218) coupled to said analog-to-digital conversion means (210), for converting said intermediate digital signals into said analog replica of said intermediate digital signals, and for coupling said analog replica to said first summing means (202); decimating filter means (108) coupled to said analog-to-digital conversion means (210) for digitally low-pass filtering said intermediate digital signals for suppressing said quantizing noise, and for generating digital output signals representing said band-limited analog signals; and resonator means (758) coupled to said analog-to-digital conversion means (210) and also coupled to said first summing means (202) for receiving said difference signals therefrom, and for filtering said analog difference signals, whereby a feedback loop is formed which tends to suppress said quantizing noise, said resonator means (758) including; (a) second summing means (762) coupled to said first summing means for receiving said difference signals therefrom and for adding to said difference signals at least first and second weighted delayed feedback signals, for generating undelayed first summed signals; (b) first weighting means (7661) coupled to an output (763) of said second summing means (762) for weighting said undelayed first summed signals by a first weight to generate weighted undelayed intermediate signals; (c) third summing means (764) coupled to said first weighting means (7661) for summing said weighted undelayed intermediate signals with at least first weighted delayed feedforward signals to produce said resonated signals; (d) a nonintegrating first cascade including the cascade of (d1) nonintegrating delay means (7681) and (d2) second weighting means (7701), said first cascade being coupled between said output (763) of said second summing means (762) for delaying and weighting said undelayed first summed signals, said delaying being by a first delay period, and said weighting being with a second weight, for producing said first weighted delayed feedback signals; (e) a nonintegrating second cascade including the cascade of (e1) nonintegrating delay means (7681) and (e2) third weighting means (7662), said second cascade being coupled between said output (763) of said second summing means (762) and an input of said third summing means (764) for delaying and weighting said undelayed first summed signals, said delaying being by a second delay period, and said weighting being with a third weight (AR2), for producing said first weighted delayed feedforward signals; (f) a nonintegrating third cascade including the cascade of (f1) nonintegrating delay means (7681, 7682) and (f2) fourth weighting means (7702), said third cascade being coupled between said output (763) of said second summing means (762) and an input of said second summing means (762) for delaying and weighting said undelayed first summed signals, said delaying being by a third delay period, and said weighting being with a fourth weight, for producing said second weighted delayed feedback signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
Specification