Double-rate sampled signal integrator

• US 5,392,043 A
• Filed: 10/04/1993
• Issued: 02/21/1995
• Est. Priority Date: 10/04/1993
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Ribner, David B.
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US08/131,537
• Time in Patent Office: 505 Days
• Field of Search: 341/143, 341/172, 341/155, 375/26-29, 375/33, 375/34
• US Class Current: 341/143
• CPC Class Codes: H03M 3/34 by chopping
• CPC Class Codes: H03M 3/342 by double sampling, e.g. correlated double sampling
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step

Abstract

A sampled signal integrator is provided comprising: an amplifier; two pairs of capacitors, the first pair of capacitors being coupled between the input and output terminals of the amplifier in a conventional negative feedback configuration, and the second pair of capacitors being coupled to the input terminals of the amplifier by a first pair of switches and likewise being coupled to a Voltage source by a second pair of switches; the two pairs of switches being further cross-coupled or synchronized to accomplish double-rate integration; and a voltage bias coupled in shunt with each of the input terminals of the amplifier to thereby provide a common mode bias to the integrator. Likewise, in another embodiment of the invention, the output signals of a sampled signal integrator configured so as to accomplish double-rate integration may be modulated and decimated to reduce or remove DC or low frequency noise.

Claims

1. A double-rate sampled signal integrator comprising:

a differential amplifier having a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal;

two capacitors, said capacitors coupling said amplifier output terminals to said amplifier input terminals so as to provide a negative feedback electrical signal;

two more capacitors, each of said two more capacitors having a first terminal and a second terminal;

two switches, each of said two switches being adapted to selectively couple the first terminal of a separate one of said two more capacitors between said amplifier input terminals;

two more switches, each of said two more switches being adapted to selectively couple the second terminal of a separate one of said two more capacitors between the terminals of an externally derived voltage source; and

a voltage bias coupled in shunt with each of said amplifier input terminals.

2. The sampled signal integrator of claim 1, wherein respective switches of said two switches are adapted to selectively couple the first terminal of respective capacitors of said two more capacitors between said amplifier input terminals so that, during one switching cycle at a substantially predetermined, externally-derived, clock rate, each respective capacitor of said two more capacitors switches amplifier input terminals.

3. The sampled signal integrator of claim 2, wherein respective switches of said two more switches are adapted to selectively couple the second terminal of respective capacitors of said two more capacitors between the terminals of an externally derived voltage source so that, during one switching cycle at the substantially predetermined, externally-derived, clock rate, each respective capacitor of said two more capacitors switches terminals of the externally derived voltage source.

4. The sampled signal integrator of claim 3, wherein the four switches are synchronized so that during one switching cycle at the substantially predetermined, externally-derived, clock rate, said two switches exchange amplifier input terminals at substantially the same time said two more switches exchange voltage source terminals.

5. The sampled signal integrator of claim 4, wherein at least one of said switches comprises a single-pole, double-throw switch.

6. The sampled signal integrator of claim 5, wherein said single-pole, double-throw switch comprises four electrically coupled CMOS transmission gates.

7. The sampled signal integrator of claim 4, wherein said voltage bias comprises at least two resistors and a bias voltage source, each of said resistors being coupled in shunt with a separate one of said amplifier input terminals and in series with said bias voltage source.

8. The sampled signal integrator of claim 4, wherein said voltage bias comprises a bias voltage source and at least two other switches and two other capacitors, each of said other capacitors having one terminal coupled to ground and having another terminal selectively coupled between said bias voltage source and a separate one of said amplifier input terminals by a separate one of said other switches.

9. The sampled signal integrator of claim 4, and further comprising two decimators, each of said amplifier decimators being coupled to a separate one of said amplifier output terminals, each of said decimators sampling the output voltage signal provided at the substantially predetermined, externally-derived, clock rate.

10. The sampled signal integrator of claim 9, wherein each of said decimators comprises a single-pole, double-throw switch adapted to selectively couple a switched capacitor between ground and the coupled amplifier output terminal at the substantially predetermined, externally-derived, clock rate.

11. A sampled signal integrator comprising:

a differential amplifier having input terminals and output terminals;

two capacitors, each of said two capacitors having a first and a second terminal;

two respective switches being adapted to selectively couple the first terminal of respective capacitors of said two capacitors between the input terminals of said amplifier;

two other respective switches being adapted to selectively couple the second terminal of respective capacitors of said two capacitors between the output terminals of said amplifier;

two more capacitors, each of said two more capacitors having a first and a second terminal;

the first terminal of each of said two more capacitors being coupled to a separate one of the input terminals of said amplifier;

two more respective switches being adapted to selectively couple the second terminal of respective capacitors of said two more capacitors between the terminals of an externally-derived voltage source;

said switches being synchronized so as to accomplish double-rate integration of a voltage signal provided by the externally-derived voltage source during one switching cycle at a substantially predetermined, externally-derived, clock rate; and

a voltage bias coupled in shunt with each of the input terminals of said amplifier.

12. A double-rate sampled signal integrator comprising:

a differential amplifier having a negative input terminal, a positive input terminal, a negative output terminal, and a positive output terminal;

six switches, each of said switches being adapted to selectively couple a first terminal between a second terminal and a third terminal;

at least two feedback capacitors, each of said feedback capacitors having two terminals;

the first and second switches of said six switches respectively selectively coupling the first terminal of the first and second capacitors of said feedback capacitors between the output terminals of said amplifier;

the third and fourth switches of said six switches respectively selectively coupling the second terminal of the first and second capacitors of said feedback capacitors between the input terminals of said amplifier;

two other capacitors, each of said other capacitors having two terminals, the first terminal of the first and second capacitors of said other capacitors being respectively coupled to the positive input terminal and the negative input terminal of said amplifier;

the fifth and sixth switches of said six switches respectively selectively coupling the second terminal of the first and second capacitors of said other capacitors between the terminals of an externally derived voltage source;

said six switches, each having a substantially predetermined, externally-derived, periodic switching cycle and being mutually synchronized so as to accomplish double-rate integration on each of said switching cycles; and

a voltage bias coupled in shunt with each of the input terminals of said amplifier.

13. A double-rate sampled signal integrator comprising:

an amplifier having at least a negative input voltage terminal, a positive input voltage terminal, and an output voltage terminal;

at least one feedback capacitor, said feedback capacitor coupling the amplifier output voltage terminal to the amplifier negative input voltage terminal to provide a negative feedback electrical signal;

two other capacitors, each of said other capacitors having two terminals;

four switches, each of said switches being adapted to selectively couple a first terminal between a second and a third terminal;

two switches of said four switches respectively selectively coupling the first terminal of respective capacitors of said two other capacitors between the terminals of an externally-derived voltage source;

two other switches of said four switches, respectively selectively coupling the second terminal of the respective capacitors of said two other capacitors between the input terminals of said amplifier;

said four switches, each having a substantially predetermined, externally-derived, periodic, switching cycle and being mutually synchronized so as to accomplish double-rate integration on each of said switching cycles; and

a voltage bias coupled in shunt with each of the input terminals of said amplifier.

14. The integrator of claim 13, and further comprising another capacitor coupling the amplifier positive input terminal to ground.

15. The integrator of claim 13, wherein at least one of said four switches comprises a single-pole, double-throw switch.

16. A double-rate sampled signal integrator comprising:

an amplifier having input-terminals and output terminals;

at least four capacitors, each of said capacitors having two terminals;

at least four switches, each of said switches being adapted to selectively couple one terminal between two other terminals; and

a common mode bias;

said common mode bias being coupled in shunt with each of the input terminals of said amplifier;

the terminals of said four capacitors and said four switches coupling an externally-derived voltage source to the amplifier input terminals and coupling the amplifier output terminals to the amplifier input terminals so as to accomplish double-rate integration of a voltage signal provided by the externally-derived voltage source on each respective switching cycle of said switches.

17. The integrator of claim 16, and further comprising a fifth switch and a sixth switch, each of said fifth switch and said sixth switch being adapted to couple one terminal between two other terminals;

and

wherein the terminals of two respective capacitors of said four capacitors each have a separate one of four switches of said six switches coupling the capacitor terminal between two terminals selected from the group consisting essentially of the amplifier input terminals and the amplifier output terminals, whereby a negative electrical feedback signal is provided from the amplifier output terminals to the amplifier input terminals; and

wherein the first terminal of two other respective capacitors of said four capacitors each have a separate one of the two remaining switches of said six respective switches respectively coupling the capacitor terminal between the terminals of the externally-derived voltage source;

the second terminal of said two other respective capacitors being respectively coupled to a separate terminal of the amplifier input terminals;

said six switches, each having a substantially predetermined, periodic, externally-derived switching cycle and being mutually synchronized so as to accomplish double-rate integration of the voltage signal on each of said switching cycles.

18. A method of performing sampled signal integration of a series of voltage signal samples of an input voltage signal with an amplifier having two input terminals and at least one output terminal, said amplifier being configured as a voltage signal integrator with at least two capacitors, each of said two capacitors being coupled to a respective one of said input terminals, the first of said capacitor coupling said at least one output terminal in a negative feedback configuration, said method comprising the steps of:

providing externally derived clock pulses at a substantially predetermined frequency, F_CL, each of said pulses having a first phase and a second phase;

sampling the input voltage signal on each phase of said clock pulses to provide the series of voltage signal samples; and

accumulating electrical charge in said capacitors by injecting electrical charge on each phase of said clock pulses, the amount of charge injected on the phase corresponding to the superposition of the voltage signal sample of the input voltage signal sampled on the phase and the voltage signal sample of the input voltage signal sampled on the immediately preceding phase.

19. The method of claim 18, wherein the accumulating step further includes the step of voltage biasing said input terminals to provide a common-mode bias for said integrator.

20. The method of claim 19, wherein said integrator produces an output voltage signal at said output terminal at least after the injected electrical charge is accumulated in said capacitors;

and

further comprising the step of decimating the output voltage signal.

21. The method of claim 20, wherein the step of decimating the output voltage signal comprises sampling the output voltage signal at the substantially predetermined frequency, F_CL.

22. The method of claim 20, wherein the step of decimating the output voltage signal comprises sampling the output voltage signal at a frequency below the substantially predetermined frequency F_CL.

23. The method of claim 19, wherein said amplifier comprises a differential amplifier, said at least one output terminal constituting a positive output voltage terminal, the output voltage signal constituting a positive output voltage signal, said differential amplifier further including a negative output voltage terminal providing a negative output voltage signal, the second of said capacitors coupling said negative output voltage terminal in a negative feedback configuration;

and

further comprising the step of periodically reversing the polarity of the provided voltage output signals at a substantially predetermined, externally-derived frequency, f_C, so as to modulate any voltage offset in the voltage output signals.

24. The method of claim 23, wherein the step of periodically reversing the polarity of the voltage output signals comprises chopper stabilizing the differential amplifier.

25. The method of claim 23, and further comprising the step of decimating respectively the negative output voltage signal and the positive output voltage signal.