Digital VCR signal processing apparatus for concealing uncorrectable errors

• US 5,392,129 A
• Filed: 06/25/1993
• Issued: 02/21/1995
• Est. Priority Date: 06/25/1992
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Juri, Tatsuro, Ohtaka, Hideki
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): TRAN, THAI Q
• Application Number:
  US08/083,052
• Time in Patent Office: 606 Days
• Field of Search: 358/314, 358/310, 358/335, 358/336, 358/37, 358/166, 360/53, 360/48, 360/33.1, 360/38.1, 360/35.1, 348/607, 348/606, 348/616
• US Class Current: 386/268
• CPC Class Codes: H04N 19/895 in combination with error concealment
• CPC Class Codes: H04N 5/9264 using transform coding
• CPC Class Codes: H04N 5/945 for signals recorded by pulse code modulation

Abstract

A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing digital signal presented in sync blocks is disclosed. Each sync block has a fixed area for low frequency data and five subsequent sync blocks define a sharing group for sharing high frequency data. The signal processing apparatus includes an inner and outer correction circuit for correcting errors in the sync blocks. An error flag is provided to a sync block which still has an error remaining after the processing in the correction circuit. A memory is provided for storing errorless sync blocks of one frame. A substitution switch is provided for passing the errorless sync blocks, but substituting a sync block stored in the memory for a sync block still having some errors. Five sync blocks produced from the substitution switch are held in a delay. When no substitute sync block is detected in the five sync blocks in the delay, the data in the five sync blocks are decoded by a bit rate reduction decoder. But, when one to four substitute sync block is detected in the five sync blocks in the delay, only the low frequency data of the five sync blocks in the fixed area are decoded by the bit rate reduction decoder.

Claims

1. A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing a digital signal presented in sync blocks each having a fixed area for storing low frequency data and an N (N is a positive integer) number of subsequent sync blocks defining a sharing group for sharing storing high frequency data, said signal processing apparatus comprising:

error correction means for correcting errors in said sync blocks;

error flag providing means for providing an error flag to a sync block which still has an error remaining after the processing in said error correction means and for selecting an errorless sync block which has no error;

memory means for storing errorless sync blocks of at least one frame;

substitution means for substituting a sync block stored in said memory means for a sync block having an error flag;

substitution detection means for detecting a presence of at least one to (N-1) substitute sync block in said N sync blocks; and

high frequency area trimming means for passing without any change said N sync blocks when no substitute sync block is detected, but for trimming the high frequency data when one to (N-1) substitute sync block is detected by said substitution detection means.

2. A signal processing apparatus as claimed in claim 1, wherein said error correction means comprises an inner correction means for correcting said errors in said sync blocks using an inner correction parity and an outer correction means for correcting said errors in said sync blocks using an outer correction parity.

3. A signal processing apparatus as claimed in claim 1, wherein said N is five.

4. A signal processing apparatus as claimed in claim 1, further comprising a bit rate reduction decoder.

5. A signal processing apparatus as claimed in claim 1, further comprising a bit rate reduction decoding means for decoding sync blocks produced from said high frequency area trimming means.

6. A signal processing apparatus as claimed in claim 5, wherein said bit rate reduction decoding means employs an orthogonal transform.

7. A signal processing apparatus for use in a digital video signal reproducing apparatus for reproducing a digital signal presented in sync blocks each having a low frequency area and a high frequency area and an N (N is a positive integer) number of subsequent sync blocks defining a sharing group for sharing high frequency areas for storing high frequency data, said signal processing apparatus comprising:

error correction means for correcting errors in said sync blocks;

error flag providing means for providing an error flag to a sync block which still has an error remaining after the processing in said error correction means and for selecting an errorless sync block which has no error;

memory means for storing errorless sync blocks of one frame;

substitution means for passing said errorless sync block and for substituting a sync block stored in said memory means for a sync block having an error flag;

holding means for holding said N number of sync blocks produced from said substitution means;

substitution detection means for detecting a presence of at least one to (N-1) substitute sync block in said N sync blocks stored in said holding means; and

high frequency area trimming means for passing without any change said N sync blocks produced from said holding means when no substitute sync block is detected, but for trimming the high frequency area from each of said N sync blocks produced from said holding means when one to (N-1) substitute sync block is detected by said substitution detection means.