Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array

• US 5,392,237 A
• Filed: 07/27/1993
• Issued: 02/21/1995
• Est. Priority Date: 09/25/1992
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Iida, Kunio
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US08/096,995
• Time in Patent Office: 574 Days
• Field of Search: 365/185, 365/52, 365/63, 365/72, 257/244, 257/315, 257/316, 257/382, 257/384, 257/385, 257/755, 257/756
• US Class Current: 365/185.16
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Provided is a semiconductor memory device wherein nonvolatile memory elements are arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are stacked on an insulating film covering a semiconductor substrate, and a source region and a drain region which are respectively formed in the semiconductor substrate on both sides of the gate electrode, the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate. The semiconductor device of such a structure is reduced in size and highly integrated with its high-performance characteristics maintained.

Claims

1. A semiconductor memory device comprising:

a plurality of nonvolatile memory elements arranged in a matrix configuration, each of the memory elements having a field effect transistor including a floating gate, an interlayer insulating film and a control gate electrode which are sequentially stacked on an insulating film covering a semiconductor substrate;

a plurality of pairs of source and drain regions respectively formed in the semiconductor substrate on both sides of the gate electrode;

polysilicon lines formed on the substrate, said polysilicon lines electrically connect the source regions; and

polysilicon electrodes formed on the drain regions upon which metal lines are connected,

wherein the floating gate, interlayer insulating film and control gate electrode being formed in a recess provided in the semiconductor substrate.

2. The semiconductor memory device of claim 1, further comprising a plurality of three-layered polysilicon structures, each having a first polysilicon film forming a source line, from one of the polysilicon lines, arranged vertically or transversely, a second polysilicon film forming said floating gate of each of said memory elements, and a third polysilicon film forming a word line through which the control gate electrodes of the memory elements arranged vertically or transversely are connected with one another.

3. The semiconductor memory device of claim 2, wherein said first and/or third polysilicon films are of a three-layered structure of doped polysilicon-tungsten silicide-polysilicon.