Addressing technique for a fault tolerant block-structured storage device
First Claim
1. A method for storing error correction code symbols in a storage array having a plurality of banks of partially defective memory devices coupled to an error correction code unit, said symbols corresponding to a block of information encoded by said error correction code unit to a code block, said method comprising the steps of:
- apportioning said error correction code symbols into a plurality of defined groups of symbols;
converting a first of said defined groups of symbols to a plurality of sets of multiple-bit words;
storing each bit of a first word within a first set of words in each memory device of a first bank at a location defined by a bank count, a row address and a column address; and
successively incrementing said column address and storing subsequent to each incremented interval each bit of successive words within said first set in each memory device of said first bank at a location defined by said row address and said successively incremented column address until all of said words within said first set are stored in said array.
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Accused Products
Abstract
A fault tolerant addressing arrangement for a solid-state disk comprising partially defective memory devices is provided. The addressing technique increments both row and column addresses when establishing locations for the storage of symbols so that the same rows and columns are not addressed for any two symbols. The technique also complements certain portions of the symbols'"'"' address to ensure addressing of different locations within each memory device.
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Citations
12 Claims
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1. A method for storing error correction code symbols in a storage array having a plurality of banks of partially defective memory devices coupled to an error correction code unit, said symbols corresponding to a block of information encoded by said error correction code unit to a code block, said method comprising the steps of:
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apportioning said error correction code symbols into a plurality of defined groups of symbols; converting a first of said defined groups of symbols to a plurality of sets of multiple-bit words; storing each bit of a first word within a first set of words in each memory device of a first bank at a location defined by a bank count, a row address and a column address; and successively incrementing said column address and storing subsequent to each incremented interval each bit of successive words within said first set in each memory device of said first bank at a location defined by said row address and said successively incremented column address until all of said words within said first set are stored in said array. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. Apparatus for storing error correction code symbols in a storage array having a plurality of banks of partially defective memory devices coupled to an error correction code unit, said symbols corresponding to a block of information encoded by said error correction code unit to a code block, said apparatus comprising:
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means for apportioning said error correction code symbols into a plurality of defined groups of symbols; means, coupled to said apportioning means, for converting a first of said defined groups of symbols to a plurality of sets of multiple-bit words; means, coupled to said converting means, for storing each bit of a first word within a first set of words in each memory device of a first bank at a location defined by a bank count, a row address and a column address; and means, coupled to said storing means, for successively incrementing said column address and means for storing subsequent to each incremented interval each bit of successive words within said first set in each memory device of said first bank at a location defined by said row address and said successively incremented column address until all of said words within said first set are stored in said array. - View Dependent Claims (9, 10, 11, 12)
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Specification