Apparatus for detecting parity errors among asynchronous digital signals
First Claim
1. A communication apparatus for an industrial control system comprising:
- means for receiving from an external device a first bit and a plurality of asynchronous digital signals in parallel, the first bit indicating a parity of the digital signals;
means for producing a first control signal when each of the asynchronous digital signals remains at a same logic level for a defined period of time, said means for producing being connected to said means for receiving;
a parity circuit coupled to said means for receiving to compute a second bit which indicates the parity of the logic levels of the digital signals, and emitting a second control signal when the first and second bits are not the same; and
means for generating an error signal in response to the presence of both the first and second control signals.
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Abstract
A communication circuit sends asynchronous digital signals in parallel to an external device. A first parity circuit in the communication circuit computes a first bit which indicates the parity of the control signals. This first bit is sent to the external device. When the digital signals and the parity bit are received by the external device, a first control signal is produced when each of the received digital signals has the same logic level for a defined period of time. A second parity circuit produces a second control signal when a parity error is found in the received digital signals. An error signal is generated in response to the presence of both the first and second control signals.
41 Citations
8 Claims
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1. A communication apparatus for an industrial control system comprising:
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means for receiving from an external device a first bit and a plurality of asynchronous digital signals in parallel, the first bit indicating a parity of the digital signals; means for producing a first control signal when each of the asynchronous digital signals remains at a same logic level for a defined period of time, said means for producing being connected to said means for receiving; a parity circuit coupled to said means for receiving to compute a second bit which indicates the parity of the logic levels of the digital signals, and emitting a second control signal when the first and second bits are not the same; and means for generating an error signal in response to the presence of both the first and second control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. In a programmable controller having a memory which stores a control program and data, a processor for executing the control program to exchange input/output data with circuits connected to a machine being controlled, and a circuit that produces a pulsed clock signal;
- the improvement comprising;
a first communication means for sending and receiving input/output data to and from another programmable controller; a second communication means for exchanging asynchronous digital control signals in parallel to the other programmable controller, each of the digital control signals having a logic level; a first parity circuit for deriving a bit which indicates the parity of the asynchronous digital control signals being sent by said second communication means; means for transmitting the bit from the first parity circuit to the other programmable controller; means for receiving a first parity signal from the other programmable controller; a first storage means for storing, in response to the clock signal, the logic level of each control signal received by said second communication means from the other programmable controller and a logic level of the first parity signal from said means for receiving, and having an output for each logic level stored therein; a second storage means for storing, in response to the clock signal, the logic levels received from the outputs of said first storage means, and said second storage means having an output for each logic level stored therein; a third storage means for storing, in response to the clock signal, the logic levels received from the outputs of said second storage means, and said third storage means having an output for each logic level stored therein; a separate comparator for each of the digital signals, each comparator having inputs coupled to said first, second and third storage means, and having an output at which an equality signal is produced when all of the stored logic levels of the corresponding digital signal are the same; means, connected to said comparators, for emitting a first control signal when all of said comparators simultaneously produce an equality signal; means for determining whether parity of the logic levels of the control signals at the outputs of said third storage means is identical to the logic level of the first parity signal stored in the third storage means, said means for determining producing a second control signal when such identity is determined; and means for generating an error signal in response to the presence of both the first and second control signals.
- the improvement comprising;
Specification