Process for fabricating submicron single crystal electromechanical structures

• US 5,393,375 A
• Filed: 12/22/1993
• Issued: 02/28/1995
• Est. Priority Date: 02/03/1992
• Status: Expired due to Term

• Current Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Original Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Inventors: Porkolab, Gyorgy A., Zhang, Zhoying L., MacDonald, Noel C.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/171,965
• Time in Patent Office: 433 Days
• Field of Search: 156/643, 437/203, 437/974, 437/978, 437/241, 148/DIG. 135
• US Class Current: 216/2
• CPC Class Codes: B81C 1/00531 Dry etching
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: Y10S 148/135 Removal of substrate

Abstract

A process for fabricating submicron movable mechanical structures utilizes chemically assisted ion beam etching and reactive ion etching which are independent of crystal orientation. The process provides released mechanical structures which may be of the same material or of different materials than the surrounding substrate, and a nitride coating may be provided on the released structure for optical applications.

Claims

1. A process for fabricating, from a single crystal substrate, a high aspect ratio, released, single-crystal microstructure having any arbitrary structural orientation with respect to the substrate, comprising:

providing a substrate of single-crystal material from which a microstructure is to be fabricated;

depositing by plasma enhanced chemical vapor deposition of silicon nitride a first layer of a dielectric stack on a top surface of said substrate;

depositing by plasma enhanced chemical vapor deposition of silicon dioxide a second layer of said dielectric stack on a top surface of said first layer;

forming in said dielectric stack a pattern of the microstructure to be fabricated;

transferring said pattern to said substrate by ion beam etching to form trenches having bottom walls and vertical side walls in the substrate, the trenches defining mesas having the location, shape and dimensions of the microstructure;

conformally coating said substrate with a dielectric material to form a third layer on said second layer, on said trench bottom walls, and on said vertical side walls;

etching back said third layer from the bottom walls of said trenches; and

releasing said mesas to produce said microstructure from said substrate.

2. The process of claim 1, further including applying a conformed layer of dielectric material to completely cover said released microstructure.

3. The process of claim 1, further including the step of metallizing selected regions of said microstructure and said substrate vertical walls.

4. The process of claim 1, further including forming a membrane over said released microstructure to provide a movable membrane.

5. The process of claim 1, wherein the step of transferring said pattern by ion beam etching includes chemically reactive ion beam etching.

6. The process of claim 1, wherein the step of transferring said pattern by ion beam etching includes reactive ion beam etching.

7. The process of claim 1, wherein the step of providing a substrate comprises selecting a single crystal material from the group consisting of gallium arsenide, silicon germanium, and indium phosphide.

8. The process of claim 1, wherein the step of providing a substrate comprises selecting a graded index, separate confinement herterostructure quantum well material.

9. The process of claim 1, wherein the step of depositing said first layer on said top surface of said substrate comprises depositing a layer having a thermal expansion matching that of said substrate material.

10. The process of claim 1, wherein the step of forming a pattern in said dielectric stack includes depositing a photoresist on said second layer, optically producing a mask pattern in said photoresist, and transferring said mask pattern by reactive ion etching to the dielectric stack through the mask pattern.

11. The process of claim 10, wherein the step of transferring said pattern to said substrate by ion beam etching includes forming trenches having smooth, vertical side walls to a depth of about 10 μ

m and smooth bottom walls in said trenches.

12. The process of claim 11, further including, after the step of forming said third layer, metallizing selected regions of said microstructure by depositing on said third layer a conformal layer of metal, masking said metal layer, and removing unmasked metal, thereby providing selected metallized regions and selected regions not coveted by said metal layer, said metal layer being removed at least from the bottoms of said trenches.

13. The process of claim 12, wherein the step of metallizing is preceded by masking, patterning and etching said third dielectric layer to provided selected contact windows therein to expose the substrate and to allow said metal to contact said substrate at selected locations.

14. The process of claim 13, wherein the step of etching back said third layer includes etching said third layer in regions not covered by said metal layer, including the bottom walls of said trenches, while leaving said third layer in place on at least parts of the side walls of said trenches, and thereafter etching the substrate at the bottoms of the trenches, deepening the trenches and laterally undercutting the mesas formed in the substrate to isolate top portions of the mesas to thereby produce said released microstructure.

15. The process of claim 14, further including applying a conformal layer of dielectric material to completely cover said released microstructure.

16. The process of claim 15, wherein the step of providing a substrate comprises selecting a gallium arsenide material.

17. The process of claim 1, wherein the step of forming a pattern includes defining a grid of mesas to be released, and further including the step of depositing a continuous membrane on top surfaces of said mesas, the membrane spanning said trenches between adjacent mesas.

18. The process of claim 1, wherein the step of forming a third dielectric layer includes depositing nitride.