Fabrication of w-polycide-to-poly capacitors with high linearity

• US 5,393,691 A
• Filed: 07/28/1993
• Issued: 02/28/1995
• Est. Priority Date: 07/28/1993
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Shung-Liang, Lin, Mou-Shiung, Lei, Ming-Dar
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/102,977
• Time in Patent Office: 580 Days
• Field of Search: 437/919, 437/60, 437/52, 437/47, 437/200
• US Class Current: 438/210
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A method of forming a polycide-to-polysilicon capacitor with a low voltage coefficient and high linearity is described. A a first layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the substrate and the field oxide regions. A layer of silicide is deposited over the polysilicon layer. The layer of silicide and the layer of polysilicon on the field oxide region are patterned, to form a polycide bottom plate of the capacitor. The polycide bottom plate is annealed. Sidewalls are formed on the sides of the polycide bottom plate. The polycide bottom plate is ion implanted in a vertical to produce the low voltage coefficient and high linearity. An interpoly dielectric layer is formed and patterned on the surface of the polycide bottom plate to act as a dielectric for the polycide-to-polysilicon capacitor. The interpoly dielectric layer is densified. A second layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the dielectric layer and on the surface of the substrate and the field oxide regions. The second layer of polysilicon is patterned to form the top plate of the capacitor.

Claims

1. A method for forming a polycide-to-polysilicon capacitor, in and on a silicon substrate, on an integrated circuit having MOSFET devices which are separated from each other by means of field oxide regions, comprising:

forming a first layer of doped polysilicon on the surface of said substrate and said field oxide regions;

depositing a layer of silicide over said first layer of doped polysilicon;

patterning said layer of silicide and said first layer of doped polysilicon on said field oxide region, to form a polycide bottom plate of said capacitor;

annealing said polycide bottom plate;

forming sidewalls on the sides of said polycide bottom plate;

ion implanting in a vertical direction into said polycide bottom plate;

forming and patterning an interpoly dielectric layer on the surface of said polycide bottom plate to act as a dielectric for said polycide-to-polysilicon capacitor;

densifying said interpoly dielectric layer;

forming a second layer of doped polysilicon on the surface of said dielectric layer and on the surface of said substrate and said field oxide regions; and

patterning said second layer of doped polysilicon to form the top plate of said capacitor.

2. The method of claim 1 wherein said ion implanting is with arsenic, in a concentration of between about 1 E 14 and 1 E 16 atoms/cm².

3. The method of claim 2 wherein said arsenic is ion implanted at an energy of between about 60 and 120 KeV.

4. The method of claim 1 wherein said silicide is tungsten silicide.

5. The method of claim 1 wherein said polycide bottom plate is annealed at a temperature of between about 850°

and 1000°

C.

6. The method of claim 1 wherein said ion implanting is with phosphorus, in a concentration of between about 1 E 14 and 1 E 16 atoms/cm², at an energy of between about 60 and 90 KeV.

7. The method of claim 1 wherein said ion implanting is with boron fluoride, in a concentration of between about 1 E 15 and 5 E 15 atoms/cm², at an energy of between about 50 and 80 KeV.

8. The method of claim 1 wherein said first layer of doped polysilicon is deposited to a thickness of between about 1500 and 2000 Angstroms.

9. The method of claim 1 wherein said first layer of doped polysilicon is doped by diffusion of POCl₃ at a temperature of between about 800°

and 920°

C.

10. The method of claim 1 wherein said layer of silicide is deposited to a thickness of between about 1500 and 2000 Angstroms.

11. The method of claim 1 wherein said interpoly dielectric layer is tetraethoxysilane (TEOS) deposited to a thickness of between about 1000 and 1400 Angstroms when used in 1-micron processing.

12. The method of claim 1 wherein said interpoly dielectric layer is tetraethoxysilane (TEOS) deposited to a thickness of between about 600 and 800 Angstroms when used in 0.6 to 0.8-micron processing.

13. The method of claim 1 wherein said intermoly dielectric layer is densified at a temperature of between about 750°

and 850°

C.

14. The method of claim 1 wherein said second layer of doped polysilicon is deposited to a thickness of between about 2500 and 3500 Angstroms.

15. A method for forming an integrated circuit in and on a silicon substrate, with a polycide-to-polysilicon capacitor and with a CMOS device with polycide gate, comprising:

forming field oxide regions, n-well and p-well regions, and gate oxide regions in and on said silicon substrate;

forming a first doped polysilicon layer on said gate oxide and said field oxide regions;

depositing a layer of silicide on said first doped polysilicon layer;

annealing said layer of silicide;

patterning said first doped polysilicon layer and said silicide layer to form gate electrode of said CMOS device, and to form a polycide bottom plate of said polycide-to-polysilicon capacitor;

forming lightly-doped drain regions in said CMOS device;

forming sidewalls on said gate electrode and on said polycide bottom plate;

ion implanting in a vertical direction into said polycide bottom plate;

ion implanting in a vertical direction into said lightly-doped drain regions of said CMOS device;

ion implanting remaining active regions of said CMOS device with a second and opposite conductivity-imparting dopant;

depositing an interpoly oxidation layer on the surfaces of said polycide bottom plate, said CMOS device, and said field oxide regions, to act as a dielectric for said polycide-to-polysilicon capacitor, and to isolate said CMOS device from subsequent layers;

densifying said interpoly oxidation layer;

forming a second doped polysilicon layer over the surface of said interpoly oxidation layer;

patterning said second doped polysilicon layer to form a polysilicon top plate of said polycide-to-polysilicon capacitor, having a suitable doping concentration; and

forming remaining layers to complete said integrated circuit.

16. The method of claim 15 wherein said ion implanting in a vertical direction of said polycide bottom plate and said lightly-doped drain regions of said CMOS device is done simultaneously.

17. The method of claim 16 wherein said ion implanting is with arsenic, in a doping concentration of between about 1 E 15 and 6 E 15 atoms/cm².

18. The method of claim 17 wherein said arsenic is ion implanted at an energy of between about 60 and 120 KeV.