Self-aligned trenched contact (satc) process

• US 5,393,704 A
• Filed: 12/13/1993
• Issued: 02/28/1995
• Est. Priority Date: 12/13/1993
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lur, Water, Huang, Cheng H.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TSAI, H JEY
• Application Number:
  US08/165,337
• Time in Patent Office: 442 Days
• Field of Search: 437/192, 437/203, 437/228, 437/41, 437/200, 148/DIG. 20
• US Class Current: 438/305
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: Y10S 148/02 Contacts, special

Abstract

A method of forming a self-aligned trenched contact in the fabrication of an integrated circuit is described. Semiconductor device regions are formed in and on a semiconductor substrate wherein the semiconductor device regions include gate electrodes on the surface of the semiconductor substrate and source/drain regions within the semiconductor substrate. Spacers are formed on the sidewalls of the gate electrodes. A layer of silicon oxide is deposited over the surface of the substrate wherein the silicon oxide contacts the source/drain regions within the substrate between the gate electrodes. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned trenched contact between the gate electrodes. The silicon oxide is etched away to provide an opening to the silicon substrate using the patterned photoresist and the sidewall spacers as a mask. A trench is etched into the silicon substrate within the opening using the photoresist and the sidewall spacers as a mask to form the self-aligned trenched contact opening. A conducting layer is deposited within the trenched opening to complete the contact in the manufacture of the integrated circuit device.

Claims

1. The method of forming a self-aligned trenched contact in the fabrication of an integrated circuit comprising:

forming semiconductor device regions in and on a semiconductor substrate wherein said semiconductor device regions include gate electrodes on the surface of said semiconductor substrate and source/drain regions within said semiconductor substrate;

forming spacers on the sidewalls of said gate electrodes;

depositing a layer of silicon oxide over the surface of said substrate wherein said silicon oxide layer contacts said source/drain regions within said substrate between said gate electrodes;

covering said substrate with a layer of photoresist and patterning said photoresist to provide an opening between said gate electrodes;

etching away said silicon oxide using said patterned photoresist and said sidewall spacers as a mask to provide an opening to said semiconductor substrate where said self-aligned trenched contact will be formed;

etching a trench into said semiconductor substrate within said opening using said sidewall spacers as a mask to form said self-aligned trenched opening wherein the depth of said trench within said semiconductor substrate is greater than about 0.25 microns and preferably greater than 0.5 microns; and

depositing a conducting layer within said trenched opening to complete said contact in the manufacture of said integrated circuit device.

2. The process of claim 1 wherein said spacers are formed by depositing a layer of silicon oxide over the surface of said semiconductor substrate and anisotropically etching said silicon oxide layer to leave spacers on the sidewalls of said gate electrodes wherein said spacers have a thickness of between about 1000 to 3000 Angstroms.

3. The process of claim 1 wherein said silicon oxide layer is deposited by chemical vapor deposition to a thickness of between about 500 to 1500 Angstroms.

4. The process of claim 1 wherein said silicon oxide layer is etched using a reactive ion etch.

5. The process of claim 1 wherein said trench is etched using a reactive ion etch.

6. The process of claim 1 wherein said conducting layer is formed by depositing a layer of polysilicon over the surface of said substrate and within said trenched opening to a thickness of between about 500 to 4000 Angstroms and wherein said polysilicon layer is ion implanted with one of the group of arsenic and phosphorus ions and wherein outdiffusion forms an N+ contact diffusion region surrounding said trench within said semiconductor substrate.

7. The process of claim 6 wherein said conducting layer further comprises a layer of tungsten silicide with a thickness of between about 500 to 2000 Angstroms overlying said polysilicon layer.

8. The process of claim 1 wherein said conducting layer is formed by depositing an in-situ doped layer of polysilicon over the surface of said substrate and within said trenched opening to a thickness of between about 500 to 4000 Angstroms and wherein outdiffusion forms an N+ contact diffusion region surrounding said trench within said semiconductor substrate.

9. The process of claim 8 wherein said conducting layer further comprises a layer of tungsten silicide with a thickness of between about 500 to 2000 Angstroms overlying said polysilicon layer.

10. The process of claim 1 wherein said conducting layer is formed by implanting one of the group of arsenic and phosphorus ions into said trench and heating said substrate to drive said ions into the region within said substrate surrounding said trench and by depositing a metal layer over the surface of said substrate and within said trench to complete said contact in the fabrication of said integrated circuit.

11. The method of claim 10 further comprising a barrier metal layer deposited conformally over the surface of said substrate and within said trench underlying said metal layer.

12. The method of claim 11 wherein said barrier metal layer is composed of titanium nitride and titanium silicide.

13. The method of claim 11 wherein said barrier metal layer is composed of titanium/tungsten.

14. The method of forming a self-aligned trenched contact in the fabrication of an integrated circuit comprising:

forming semiconductor device regions in and on a semiconductor substrate wherein said semiconductor device regions include gate electrodes on the surface of said semiconductor substrate and source/drain regions within said semiconductor substrate;

forming spacers on the sidewalls of said gate electrodes;

depositing a layer of silicon oxide over the surface of said substrate wherein said silicon oxide layer contacts said source/drain regions within said substrate between said gate electrodes;

covering said substrate with a layer of photoresist and patterning said photoresist to provide an opening between said gate electrodes;

etching away said silicon oxide using said patterned photoresist and said sidewall spacers as a mask to provide an opening to said semiconductor substrate where said self-aligned trenched contact will be formed;

etching a trench into said semiconductor substrate within said opening using said sidewall spacers as a mask to form said self-aligned trenched opening wherein the depth of said trench within said semiconductor substrate is greater than about 0.25 microns and preferably greater than 0.5 microns; and

depositing a layer of polysilicon over the surface of said substrate and within said trenched opening wherein said polysilicon layer is ion implanted and wherein outdiffusion forms an N+ contact diffusion region surrounding said trench within said semiconductor substrate to complete said contact in the manufacture of said integrated circuit device.

15. The process of claim 14 wherein said spacers are formed by depositing a layer of silicon oxide over the surface of said semiconductor substrate and anisotropically etching said silicon oxide layer to leave spacers on the sidewalls of said gate electrodes wherein said spacers have a thickness of between about 1000 to 3000 Angstroms.

16. The process of claim 14 wherein silicon oxide layer is deposited by chemical vapor deposition to a thickness of between about 500 to 1500 Angstroms.

17. The process of claim 14 wherein a layer of tungsten silicide with a thickness of between about 500 to 2000 Angstroms is deposited overlying said polysilicon layer.

18. The method of forming a self-aligned trenched contact in the fabrication of an integrated circuit comprising:

forming semiconductor device regions in and on a semiconductor substrate wherein said semiconductor device regions include gate electrodes on the surface of said semiconductor substrate and source/drain regions within said semiconductor substrate;

forming spacers on the sidewalls of said gate electrodes;

depositing a layer of silicon oxide over the surface of said substrate wherein said silicon oxide layer contacts said source/drain regions within said substrate between said gate electrodes;

covering said substrate with a layer of photoresist and patterning said photoresist to provide an opening between said gate electrodes;

etching away said silicon oxide using said patterned photoresist and said sidewall spacers as a mask to provide an opening to said semiconductor substrate where said self-aligned trenched contact will be formed;

etching a trench into said semiconductor substrate within said opening using said sidewall spacers as a mask to form said self-aligned trenched opening wherein the depth of said trench within said semiconductor substrate is greater than about 0.25 microns and preferably greater than 0.5 microns;

implanting ions into said trench and heating said substrate to drive said ions into the region within said substrate surrounding said trench; and

depositing a metal layer over the surface of said substrate and within said trench to complete said contact in the manufacture of said integrated circuit device.

19. The process of claim 18 wherein said spacers are formed by depositing a layer of silicon oxide over the surface of said semiconductor substrate and anisotropically etching said silicon oxide layer to leave spacers on the sidewalls of said gate electrodes wherein said spacers have a thickness of between about 1000 to 3000 Angstroms.

20. The process of claim 18 wherein silicon oxide layer is deposited by chemical vapor deposition to a thickness of between about 500 to 1500 Angstroms.

21. The method of claim 18 further comprising a barrier metal layer deposited conformally over the surface of said substrate and within said trench underlying said metal layer.

22. The method of claim 21 wherein said barrier metal layer is composed of titanium nitride and titanium silicide.

23. The method of claim 21 wherein said barrier metal layer is composed of titanium/tungsten.