Package structure for semiconductor devices and method of manufacturing the same

• US 5,394,011 A
• Filed: 07/06/1993
• Issued: 02/28/1995
• Est. Priority Date: 06/20/1991
• Status: Expired due to Term

• Current Assignee: Fuji Electrochemical Company Limited, Iwaki Electronics Company Limited
• Original Assignee: Fuji Electrochemical Company Limited, Iwaki Electronics Company Limited
• Inventors: Sato, Kaori, Yamamoto, Hiroyasu, Suzuki, Hiroyoshi, Konuma, Takayuki, Shika, Akira, Katouno, Masanori
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): MONIN, DONALD L JR
• Application Number:
  US07/972,459
• Time in Patent Office: 602 Days
• Field of Search: 257/668, 257/678, 257/690, 257/692, 257/693, 257/698, 257/700, 257/701, 257/703, 257/704, 257/729, 257/772, 257/786, 257/758, 257/710
• US Class Current: 257/693
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/0103 Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A package structure in which conductive layers are provided on the lower surface of a circuit substrate provided with a semiconductor element mounted on the upper surface thereof, which conductive layers are connected to a conductive seal portion via conductive through holes, whereby both satisfactory air-tightness and satisfactory electromagnetic shielding characteristics of the package structure can be obtained. Projections consisting of high-temperature solder are formed as externally connecting electrodes, whereby a surface packaging operation can be carried out smoothly.

Claims

1. A package structure for a semiconductor device having a lead electrode comprising:

an electrically conductive cap having a flange at a circumference thereof,

a circuit substrate having a ceramic substrate member, a first surface covered with said conductive cap and sealed air-tightly, a second surface having electrically conductive patterns for providing thereon external electrodes, and projections of high-temperature solder having a melting point of approximately 240°

-330°

C. are formed on said conductive patterns,

wherein said circuit substrate comprises;

a first electrically conductive layer on said first surface of said circuit substrate extending along an outer circumference of said circuit substrate,

a second electrically conductive layer covering said second surface of said circuit substrate, said second conductive layer being formed substantially entirely over said second surface of said circuit substrate except having a portion for said lead electrode of said semiconductor device,

a plurality of electrically conductive through-holes, disposed uniformly in said circuit substrate directly below said first conductive layer and said flange, for connecting said first conductive layer with said second conductive layer, and

electrically conductive sealing means for sealing contact surfaces of said flange of the conductive cap to said first conductive layer.

2. A package structure according to claim 1, wherein the projections of high temperature solder have heights in a range of 0.2-1.0 mm.

3. A package structure according to claim 1, wherein said conductive patterns for providing thereon said external electrodes have a circular shape.

4. A package structure according to claim 1, wherein said conductive patterns for providing thereon said external electrodes are defined by an electrically conductive material.

5. A package structure according to claim 1, wherein each of said projections of high-temperature solder is formed frusto-hemispherically to provide a flat surface at free end portion thereof.

6. A package structure according to claim 1, wherein a metallized layer is formed to provide an electrically conductive pattern, and said projections of the high-temperature solder are formed on said metallized layer.