Electrically alterable non-voltatile memory with N-bits per memory cell

• US 5,394,362 A
• Filed: 06/04/1993
• Issued: 02/28/1995
• Est. Priority Date: 02/08/1991
• Status: Expired due to Term

• Current Assignee: BTG International Inc. (Boston Scientific Corporation)
• Original Assignee: Gerald J. Banks
• Inventors: Banks, Gerald J.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/071,816
• Time in Patent Office: 634 Days
• Field of Search: 365/168, 365/185, 365/45, 365/189.01
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The bit storage density of an Electrically Alterable Non-Volatile Memory (EANVM) cell is improved by increasing the number of bits that are stored on an individual memory cell, without increasing the size and complexity of the memory cell, by allowing a non-volatile memory cell to assume 2 n discrete memory states. A multi-bit memory cell uses a floating gate FET which is electrically programmed to 2 n different thresholds. The 2 n different conductivity states of the FET are provided as information storage states for the cell.

Claims

1. An electrically alterable non-volatile multi-level memory device, comprising:

a non-volatile, multi-level memory cell means for storing input information for an indefinite perios of time as a discrete state of said memory cell means, said memory cell means includes more than two memory states;

memory cell programming means for programming the memory state of said multi-level memory cell means to a predetermined state corresponding to input information to be stored in said memory cell means; and

comparator means for comparing the memory state of said memory cell means with the input information to be stored in said memory and for generating a control signal indicative of the memory state of said memory cell;

wherein said memory cell includes a gate which has an applied voltage being set to one of a plurality of voltage levels by said memory cell programming means corresponding to the input information.

2. An electrically alterable non-volatile multi-level memory device, comprising:

a multi-level memory cell including a floating gate FET having a channel region connected between an output terminal and a terminal for a first reference voltage, said FET having a floating gate for storing electrons which modify the voltage threshold of said FET and which controls the conductivity of the channel region of the FET;

means for storing electrons on the floating gate so that the conductivity state of the channel region of the FET is within one of K n pre-determined conductivity ranges where K is the base of the numbering system being used and n is the number of bits per cell and the result of K n is greater than two; and

comparator means for comparing a representation of the conductivity state of the channel region of said memory cell with a representation of an n-bit input signal to be stored in the memory cell;

wherein said floating gate of said memory cell has an applied voltage which is set to one of a plurality of voltage levels by said electron storing means corresponding to input information.

3. An electrically alterable non-volatile multi-level memory array, comprising:

an M×

N array of multi-level memory cells, each memory cell including a floating gate FET having a channel region coupled between a bit-line output terminal and a terminal for a first reference voltage, having a floating gate for storing charge and for controlling the conductivity of the channel region of the FET, and having a selection gate terminal connected to an output line of a row selection circuit for activating said memory cell, each memory cell includes more than two memory states;

means for electrically establishing the voltage threshold of the FET cell within a pre-determined range of conductivity of said channel region by storing electrons on the floating gate; and

means for comparing the voltage at the bit-line terminal with an n-bit input signal which represents an n-bit digital input signal to be stored in each memory cell;

wherein said floating gate of each memory cell has an applied voltage which is set to one of a plurality of voltage levels by said electrically establishing means corresponding to input information.