Charge pump circuit having an improved charge pumping efficiency

• US 5,394,365 A
• Filed: 04/12/1993
• Issued: 02/28/1995
• Est. Priority Date: 04/16/1992
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tsukikawa, Yasuhiko
• Primary Examiner(s): Yoo, Do Hyun
• Application Number:
  US08/045,069
• Time in Patent Office: 687 Days
• Field of Search: 365/189.09, 365/204, 365/177, 307/578, 307/607, 307/264, 307/482, 307/296.2
• US Class Current: 365/189.09
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/078 with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters

Abstract

A charge pump circuit includes a P channel field effect transistor, a diode-connected N channel field effect transistor between a first node and a second node. The P channel field effect transistor operates in response to a first clock signal applied through a first capacitor to discharge the first node to a ground potential. The first node receives a second clock signal through a second capacitor. Negative electric charges are pumped out to the second node. A negative bias voltage is generated from the second node with an improved efficiency and reliability.

Claims

1. A charge pump circuit for generating a predetermined voltage, comprising:

a first transistor element responsive to a first clock signal applied through first capacitance means for transferring a first reference voltage to a first node, said first node receiving a second clock signal through capacitive coupling of second capacitance means; and

a rectifying element connected between the first node and a second node such that electric charges required for generating said predetermined voltage are unidirectionally transferred, said rectifying element comprising a diode-connected transistor element different in conductivity type from said first transistor element.

2. The charge pump circuit according to claim 1, wherein

said first transistor element comprises an insulated gate type field effect transistor of a first conductivity type, and said rectifying element comprises an insulated gate type field effect transistor of a second conductivity type opposite to said first conductivity type connected in a diode fashion.

3. The charge pump circuit according to claim 2, wherein

said insulated gate type field effect transistor of the second conductivity type has one conduction terminal connected to said first node, and another conduction terminal and a control gate and a bulk connected together to said second node.

4. The charge pump circuit according to claim 2, wherein

said insulated gate type field effect transistor of the first conductivity type has one conduction terminal connected to receive said reference voltage, another conduction terminal connected to said first node, and a control gate connected to receive the first clock signal through said first capacitance means.

5. The charge pump circuit according to claim 1, wherein said reference voltage is a voltage at a level of a ground potential, said predetermined voltage is a negative voltage lower than said ground potential, and said electric charges are electrons.

6. The charge pump circuit according to claim 2, wherein

said reference voltage is a voltage at a level of a ground potential, and said predetermined voltage is a negative voltage lower than the ground potential, and wherein

said first conductivity type is P type, and said second conductivity type is N type.

7. The charge pump circuit according to claim 2, wherein

said rectifying element is formed in a first conductivity type well region surrounded by a semiconductor layer of the second conductivity type and separated from any other region for forming an element.

8. The charge pump circuit according to claim 7, wherein

said first conductivity type well region is connected to said second node.

9. The charge pump circuit according to claim 1, wherein said reference voltage is an operating power supply voltage, and said predetermined voltage is a boosted voltage higher than said operating power supply voltage, and said electric charges are holes.

10. The charge pump circuit according to claim 2, wherein

said reference voltage is an operating power supply voltage, and

said predetermined voltage is a boosted voltage higher than said operating power supply voltage, and wherein said first conductivity type is N type, and said second conductivity type is P type.

11. The charge pump circuit according to claim 1, wherein said predetermined voltage is a negative voltage which is applied to a P type semiconductor layer serving as a substrate of a memory device.

12. The charge pump circuit according to claim 1, wherein said predetermined voltage is a boosted voltage utilized in a memory device.

13. The charge pump circuit according to claim 12, wherein said boosted voltage is used for driving a selected word line connecting a row of memory cells in said memory device.

14. The charge pump circuit according to claim 11, wherein said charge pump circuit is integrated in said memory device.

15. The charge pump circuit according to claim 14, wherein said memory device is a random access memory device.

16. The charge pump circuit according to claim 1, further comprising a transistor element having one conduction terminal connected to receive the first clock signal through said first capacitance means, and another conduction terminal and a control gate connected together to receive said reference voltage.

17. The charge pump circuit according to claim 12, wherein said charge pump circuit is integrated in said memory device.

18. A charge pump circuit for generating a predetermined voltage comprising:

a first gate type field effect transistor of a first conductivity type responsive to a first clock signal applied through first capacitance means for transferring a first reference voltage to a first node, said first node receiving a second clock signal through capacitive coupling of second capacitance means; and

a rectifying element connected between the first node and a second node such that electric charges required for generating said predetermined voltage are unidirectionally transferred, said rectifying element comprising;

a junction diode and,

wherein said junction diode is formed in a well region of the first conductivity type surrounded by a semiconductor layer of a second conductivity type and separated from any other region forming an element.

19. The charge pump circuit according to claim 18, wherein said well region provides an anode region of the junction diode.

20. The charge pump circuit according to claim 18, wherein said well region provides a cathode region of the junction diode.