System and method for write-protecting predetermined portions of a memory array
First Claim
1. A method for write-protecting predetermined portions of a memory array utilizing a number of lock bits settable for controlling subsequent writes to selected ones of said predetermined portions of said memory array, said method comprising the steps of:
- defining a first memory location for containing a known value forming a soft fuse value and a second memory location for containing said lock bits;
reading the contents of said first memory location to determine a read-out contents thereof;
comparing said read-out contents of said first memory location to said soft fuse value;
allowing setting and resetting of individual ones of said lock bits if said read-out contents do not correspond to said soft fuse value; and
allowing setting and disallowing resetting of individual ones of said lock bits if said read-out contents correspond to said soft fuse value.
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Accused Products
Abstract
A system and method wherein a predetermined soft fuse value may be written to a corresponding soft fuse register to control subsequent access to a number of lock bits in a non-volatile semiconductor memory array which are provided for selectively precluding writes to predetermined portions of the memory array. In a specific embodiment, the system and method may be utilized in conjunction with radio frequency ("RF") identification ("ID") transponders incorporating a non-volatile ferroelectric random access memory ("FRAM") array integrated circuit.
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Citations
21 Claims
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1. A method for write-protecting predetermined portions of a memory array utilizing a number of lock bits settable for controlling subsequent writes to selected ones of said predetermined portions of said memory array, said method comprising the steps of:
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defining a first memory location for containing a known value forming a soft fuse value and a second memory location for containing said lock bits; reading the contents of said first memory location to determine a read-out contents thereof; comparing said read-out contents of said first memory location to said soft fuse value; allowing setting and resetting of individual ones of said lock bits if said read-out contents do not correspond to said soft fuse value; and allowing setting and disallowing resetting of individual ones of said lock bits if said read-out contents correspond to said soft fuse value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit including a memory array having predetermined write-protectable portions thereof utilizing a number of lock bits settable for controlling subsequent writes to selected ones of said write-protectable portions, said memory array comprising:
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first and second memory locations for containing a known value forming a soft fuse value and said lock bits respectively; means, coupled to said first memory location, for comparing;
coupled to said first memory location, for reading the contents of said first memory location to determine a read-out contents thereof;means, coupled to receive said soft fuse value and said read-out contents, for comparing said read-out contents of said first memory location to said soft fuse value; means, coupled to said second memory location and responsive to said means for comparing, for allowing setting and resetting of individual ones of said lock bits if said read-out contents do not correspond to said soft fuse value; and means, coupled to said second memory location and resposive to said means for comparing for allowing setting and disallowing resetting of individual ones of said lock bits if said read-out contents correspond to said soft fuse value. - View Dependent Claims (9, 10, 11, 12, 13)
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14. An RF transponder including a memory array having predetermined write-protectable portions thereof utilizing a number of lock bits settable for controlling subsequent writes to selected ones of said write-protectable portions, said memory array comprising:
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first and second memory locations for containing a known value forming a soft fuse value and said lock bits respectively; means, coupled to said first memory location, for reading the contents of said first memory location to determine a read-out contents thereof; means, coupled to receive said soft fuse value and said read-out contents, for comparing said read-out contents of said first memory location to said soft fuse value; means, coupled to said second memory location and responsive to said means for comparing, for allowing setting and resetting of individual ones of said lock bits if said read-out contents do not correspond to said soft fuse value; and means, coupled to said second memory location and responsive to said means for comparing, for allowing setting and disallowing resetting of individual ones of said lock bits if said read-out contents correspond to said soft fuse value. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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Specification