Universal weight generator
First Claim
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1. A circuit for generating a controllably weighted binary sequence, said circuit comprising:
- means for generating a first plurality, said first plurality being N, of pseudo-random binary signal sequences; and
a second plurality, said second plurality also being N, of logic circuit stages, wherein each of said stages receives one of said binary sequences from said generating means, and wherein each of said stages also receives a specifiable weighting control signal, said stages being cascaded so that the output of each stage is supplied as input to its subsequent stage; and
wherein each stage includes conjunctive circuit means having as input said preceding stage output and one of said pseudo-random binary signal sequences, with the output of said conjunctive circuit means being supplied to conditional inverter circuit means which also has an input said specifiable weighing control signal and whose output is supplied to the conjunctive circuit means in said subsequent stage.
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Abstract
A cascaded arrangement of alternating AND gates and Exclusive-OR gates is employed in conjunction with an output from a pseudo-random signal generator to produce a weighted random pattern binary sequence which is granularly controllable in terms of user selected probabilities and for which the granularity level is readily controlled through the selection of a desirable number of cascaded stages.
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Citations
1 Claim
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1. A circuit for generating a controllably weighted binary sequence, said circuit comprising:
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means for generating a first plurality, said first plurality being N, of pseudo-random binary signal sequences; and a second plurality, said second plurality also being N, of logic circuit stages, wherein each of said stages receives one of said binary sequences from said generating means, and wherein each of said stages also receives a specifiable weighting control signal, said stages being cascaded so that the output of each stage is supplied as input to its subsequent stage; and wherein each stage includes conjunctive circuit means having as input said preceding stage output and one of said pseudo-random binary signal sequences, with the output of said conjunctive circuit means being supplied to conditional inverter circuit means which also has an input said specifiable weighing control signal and whose output is supplied to the conjunctive circuit means in said subsequent stage.
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsSavir, Jacob
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Primary Examiner(s)Beausoliel, Jr., Robert W.
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Assistant Examiner(s)Decady, Albert
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Application NumberUS07/873,131Time in Patent Office1,040 DaysField of Search371/27, 371/15.1, 371/22.3, 371/25.1, 364/717US Class Current714/739CPC Class CodesG01R 31/31813 Test pattern generatorsG01R 31/318385 Random or pseudo-random tes...G06F 11/277 with comparison between act...G06F 7/582 Pseudo-random number genera...
