Lock detect circuit for detecting a lock condition in a phase locked loop and method therefor

• US 5,394,444 A
• Filed: 07/12/1993
• Issued: 02/28/1995
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Smallwood, J. Christopher, Silvey, John M.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/088,951
• Time in Patent Office: 596 Days
• Field of Search: 375/118, 375/119, 375/120, 328/155, 328/63, 328/134, 307/510, 307/511
• US Class Current: 375/374
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth

Abstract

A lock detect circuit (18) determines when a reference frequency and a feedback frequency are frequency locked using a reference counter (32) and a feedback counter (36). The reference counter (32) and the feedback counter (36) are clocked by the reference frequency and the feedback frequency, respectively. After a first period of time, the outputs of the counters are compared. The outputs of the counters are also compared at the end of a second period of time. To be frequency locked, the two count values must be equal at both the end of the first and the second periods of time. A count window is generated from the reference frequency signal to indicate a range of frequencies for which the feedback frequency is locked. Once lock is achieved, the count window is widened such that the feedback frequency is still within a lock range when some aliasing occurs.

Claims

1. A lock detect circuit, comprising:

first input means for receiving a reference frequency;

second input means for receiving a feedback frequency;

a reference counter coupled to the first input means for receiving the reference frequency, the reference counter counting to a reference count value during a first period of time, the reference counter providing a freeze signal to indicate the reference counter has reached the reference count value;

a feedback counter coupled to the second input means for receiving the feedback frequency, the feedback counter counting for the first period of time to generate a feedback count value;

comparison means for comparing the feedback count value to the reference count value, the comparison means asserting a first match signal when the feedback count value is one of a range of lock values determined by the reference count value and a locked signal is asserted to indicate the first match signal is asserted for a second and a third period of time, the third period of time successively following the second period of time, the comparison means being coupled to the feedback counter for receiving the feedback count value; and

a match detector coupled to the comparison means for providing the locked signal, the match detector asserting the locked signal when the comparison means asserts the first match signal for both the second period of time and the third period of time.

2. The lock detect circuit of claim 1 further comprising:

a counter control circuit coupled to the reference counter for receiving the freeze signal, the counter control circuit providing a toggle signal to indicate the reference count value is one of a first count value and a second count value, wherein the first count value is not harmonically related to the second count value.

3. The lock detect circuit of claim 2 wherein the first match signal is asserted during the second period of time when the feedback count value is equal to the first count value.

4. The lock detect circuit of claim 2 wherein a second match signal is asserted during the third period of time when the feedback count value is equal to the second count value.

5. The lock detect circuit of claim 1 wherein each of the range of lock values is equal to a preselected percentage of the reference count value.

6. The lock detect circuit of claim 1 further comprising:

an auxiliary control generator for generating a kickoff signal in response to the locked signal, the kickoff signal being used to operate a charge pump external to the lock detect circuit, the auxiliary control generator being coupled to the match detector for receiving the locked signal.

7. The lock detect circuit of claim 6 wherein the comparison means comprises:

a first comparator for comparing the feedback count value to an auxiliary count value, the first comparator asserting a kickoff control signal to indicate that the feedback count value is equal to the auxiliary count value, the first comparator negating the kickoff control signal to indicate that the feedback count value is not equal to the auxiliary count value.

8. The lock detect circuit of claim 1 wherein the reference frequency is provided by a crystal oscillator external to the lock detect circuit.

9. The lock detect circuit of claim 1 wherein the feedback frequency is provided by a voltage controlled oscillator external to the lock detect circuit.

10. A method for detecting lock in a phase lock loop circuit, comprising the steps of:

i) receiving a reference frequency signal;

ii) receiving a feedback frequency signal;

iii) enabling a reference counter to count for a first period of time using the reference frequency signal, the reference counter providing a first reference count value;

iv) concurrently enabling a feedback counter to count for the first period of time using the feedback frequency signal, the feedback counter providing a first feedback count value;

v) comparing the first reference count value and the first feedback count value to provide a first match signal;

vi) providing the first match signal to a match detect circuit, the match detect circuit storing the first match signal therein;

vii) enabling the reference counter to count for a second period of time using the reference frequency signal, the reference counter providing a second reference count value;

viii) concurrently enabling the feedback counter to count for the second period of time using the feedback frequency signal, the feedback counter providing a second feedback count value;

ix) comparing the second reference count value and the second feedback count value to provide a second match signal, the second match signal being asserted when the second feedback count value is equal to the second reference count value and the locked signal is not asserted; and

x) providing the second match signal to the match detect circuit, the match detect circuit asserting the locked signal when both the first match signal and the second match signal are asserted.

11. The method of claim 10 further comprising the steps of:

xi) enabling the reference counter to count for the first period of time using the reference frequency signal, the reference counter providing the first reference count value;

xii) concurrently enabling the feedback counter to count for the first period of time using the feedback frequency signal, the feedback counter providing a third feedback count value;

xiii) comparing the first reference count value and the third feedback count value to provide a third match signal, the third match signal being asserted when the third feedback count value is one of a first count value range and the locked signal is asserted to indicate the third match signal is asserted for a second and a third period of time, the third period of time successively following the second period of time, the third match signal being negated when the third feedback count value is not one of the first count value range;

xiv) if the third match signal is not asserted, repeating each of steps i) through x);

xv) if the third match signal is asserted, providing the third match signal to the match detect circuit, the match detect circuit storing the third match signal therein;

xvi) enabling the reference counter to count for the second period of time using the reference frequency signal, the reference counter providing the second reference count value;

xvii) concurrently enabling the feedback counter to count for the second period of time using the feedback frequency signal, the feedback counter providing a fourth feedback count value;

xviii) comparing the second reference count value and the fourth feedback count value to provide a fourth match signal, the fourth match signal being asserted when the fourth feedback count value is one of a second count value range and the locked signal is asserted; and

xix) if the fourth match signal is negated, repeating each of steps i) through x); and

xx) if the fourth match signal is asserted, providing the fourth match signal to the match detect circuit, the match detect circuit allowing the locked signal to remain asserted when both the third match signal and the fourth match signal are asserted.

12. The method of claim 11 wherein the first count value range comprises a first plurality of count values wherein each of the first plurality of count values corresponds to a preselected percentage of the first reference count value.

13. The method of claim 11 wherein the second count value range comprises a second plurality of count values wherein each of the second plurality of count values corresponds to a preselected percentage of the second reference count value.

14. The method of claim 10 wherein the first period of time and the second period of time are not harmonically related.

15. A phase lock loop system, comprising:

first interface means for receiving a reference frequency signal;

second interface means for receiving a feedback frequency signal;

a phase comparator for comparing a phase of the reference frequency signal to a phase of the feedback frequency signal, the phase comparator providing a frequency control signal in response to a difference between the phase of the reference frequency signal and the phase of the feedback frequency signal, the phase comparator having a first input coupled to the first interface means for receiving the reference frequency signal, the phase comparator having a second input coupled to the second interface means for receiving the feedback frequency signal;

a charge pump coupled to the phase comparator for receiving the frequency control signal, the charge pump providing a voltage value in response to the frequency control signal;

a voltage controlled oscillator coupled to the charge pump for receiving the voltage value, the voltage controlled oscillator providing the feedback frequency signal, the feedback frequency signal being determined in response to the voltage value; and

a lock detect circuit for detecting when the feedback frequency signal is locked to the reference frequency signal, the lock detect circuit asserting a locked signal to indicate when the feedback frequency signal is locked to the reference frequency signal, wherein the lock detect circuit comprises;

a reference counter coupled to the first interface means for receiving the reference frequency signal, the reference counter counting to a reference count value during a first period of time, the reference counter providing a freeze signal to indicate the reference counter has reached the reference count value;

a feedback counter coupled to the second interface means for receiving the feedback frequency signal, the feedback counter counting for the first period of time to generate a feedback count value;

comparison means for comparing the feedback count value to the reference count value, the comparison means asserting asserting a match signal when the feedback count value is one of a range of lock values and a locked signal is asserted to indicate the match signal is asserted for a second and a third period of time, the third period of time successively following the second period of time, the comparison means being coupled to the feedback counter for receiving the feedback count value;

a match detector coupled to the comparison means for providing the locked signal, the match detector asserting the locked signal when the comparison means asserts a first and a second match signal, the first and the second match signals being successively asserted; and

an auxiliary control generator for generating an auxiliary control signal for enhancing operation of the charge pump, the auxiliary control signal being asserted when the feedback count value is equal to an auxiliary count value.

16. The phase lock loop system of claim 15 wherein the auxiliary count value is a preselected percentage of the reference count value.

17. The phase lock loop system of claim 15 wherein the asserted auxiliary control signal enables the charge pump to output an enhanced voltage value, the enhanced voltage value having a higher value than the voltage value provided by the charge pump when the auxiliary control signal is negated.

18. The phase lock loop system of claim 15 further comprising:

a status register for storing a lock status bit, the lock status bit corresponding to a logic state of the locked signal, the status register being coupled to the lock detect circuit for receiving the locked signal.

19. The phase lock loop system of claim 15 further comprising:

a counter control circuit coupled to the reference counter for receiving the freeze signal, the counter control circuit providing a toggle signal to indicate the reference count value is one of a first count value and a second count value, wherein the first count value is not harmonically related to the second count value.